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Home
學術出版;;Publications
研究計畫;;Research Plans
對以智財單元為基系統晶片設計之驗證與測試技術開發研究---子計畫IV:以智財單元為基系統晶片設計之測試技術研究
對以智財單元為基系統晶片設計之驗證與測試技術開發研究---子計畫IV:以智財單元為基系統晶片設計之測試技術研究
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902215E009084.pdf
(288.05 KB)
902215E009084.pdf
(288.05 KB)
Date
2001
Authors
李崇仁
Journal Title
Journal ISSN
Volume Title
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DOI
Abstract
Description
Keywords
系統晶片
,
晶片設計
,
測試技術
,
System-on-chip (SOC)
,
Chip design
,
Test technique
Citation
URI
https://www.grb.gov.tw/search/planDetail?id=665767&docId=126390
https://ir.lib.nycu.edu.tw/handle/11536/93688
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