雙埠次臨界靜態隨機存取記憶體單元

dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumberI470631zh_TW
dc.contributor.author邱議德en_US
dc.contributor.author張銘宏en_US
dc.contributor.author楊皓義en_US
dc.contributor.author黃威en_US
dc.date.accessioned2015-05-12T03:00:00Z
dc.date.available2015-05-12T03:00:00Z
dc.date.issued2015-01-21en_US
dc.description.abstract本發明係提供一種創新的雙埠次臨界靜態隨機存取記憶體(static random access memory,下稱SRAM)單元,適用於次臨界電壓(substhreshold voltage)下操作。本發明之雙埠次臨界SRAM單元在寫入時,會切斷記憶元件之正回授,並應用反短通道效應(reverse short-channel effect,RSCE)增強寫入能力。而本發明單端讀寫的架構更能夠進一步降低長位線(long bit line)所造成的功率消耗,因此更適合應用於長時間工作之先進先出(first-in first-out,FIFO)記憶體設計。據此,本發明之SRAM單元在次臨界電壓下仍然能夠提供穩定的操作,解決習知記憶體單元因降低電壓而造成穩定度下降的問題。zh_TW
dc.identifier.govdocG11C011/413zh_TW
dc.identifier.govdocG11C008/04zh_TW
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/122925
dc.language.isozh_TWen_US
dc.title雙埠次臨界靜態隨機存取記憶體單元zh_TW
dc.typePatentsen_US

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