A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

dc.citation.epage116en_US
dc.citation.spage115en_US
dc.contributor.authorYih, CMen_US
dc.contributor.authorChung, SSen_US
dc.contributor.authorHsu, CCHen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:27:35Z
dc.date.available2014-12-08T15:27:35Z
dc.date.issued1996en_US
dc.identifier.isbn0-7803-2745-4en_US
dc.identifier.journalSISPAD '96 - 1996 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICESen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/19842
dc.identifier.wosnumberWOS:A1996BG48K00053
dc.language.isoen_USen_US
dc.titleA numerical model for simulating MOSFET gate current degradation by considering the interface state generationen_US
dc.typeProceedings Paperen_US

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