ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications

Abstract

On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2 similar to 3nA), low trigger voltage (similar to 2V), high ESD robustness (>8kV), and free to latchup issue.