An improved AVPG algorithm for SoC design verification using port order fault model

Abstract

Embedded cores are being increasingly used in the design of large System-on-a-Chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrator To reduce the verification complexity, the Port order fault (POF) model proposed in [1] has been used for verifying core-based designs and the corresponding verification pattern generation have been developed [2] [3]. Here we present in automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) proposed in [3] for SoC design verification based on POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the results of AVPG.