Data line driver design for a 10'' 480x640x3 color FED

Abstract

A data line driver with 120 outputs and capable of producing contrast ratio over 100 for a 10'' 480x(640x3) pixels color field emission display (FED) panel have been designed. Three phase clocks were used to reduce the maximum operating frequency to 22.68Mhz. A class AB Op Amp was used as the analog output buffer to reduce the power dissipation. The chip is implemented in a 24V CMOS process, chip size is 7620 mu m x 17500 mu m.