Browsing by Author "Bhadra, Jayanta"

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An incremental learning framework for estimating signal controllability in unit-level verification
(2007)
Wen, Charles H. -P.
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Wang, Li-C.
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Bhadra, Jayanta
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電信工程研究所
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Institute of Communications Engineering
Unit-level verification is a critical step to the success of full-chip functional verification for microprocessor designs. In the unit-level verification, a unit is first embedded in a complex software that emulates the behavior of surrounding units, and then a sequence of stimuli is applied to measure the functional coverage. In order to generate such a sequence, designers need to comprehend the relationship between boundaries at the unit under verification and at the inputs to the emulation software. However, figuring out this relationship can be very difficult. Therefore, this paper(1) proposes an incremental learning framework that incorporates an ordered-binary-decision-forest(OBDF) algorithm, to automate estimating the controllability of unit-level signals and to provide full-chip level information for designers to govern these signals. Mathematical analysis shows that the proposed OBDF algorithm has lower model complexity and lower error variance than the previous algorithms. Meanwhile, a commercial microprocessor core is also applied to demonstrate that controllability of input signals on the load/store unit in the microprocessor core can be estimated automatically and information about how to govern these signals can also be extracted successfully.
An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
(2012)
Chang, Chia-Ling (Lynn)
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Chang, Chia-Ching (Austin)
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Chan, Hui-Ling
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Wen, Charles H. -P.
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Bhadra, Jayanta
Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named sigma-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that sigma-Iddq testing achieves a higher classification accuracy in a 45nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.
Portable simulation/emulation stimulus on an industrial-strength SoC
(2009)
Torres, Francisco
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Srivastava, Rohit
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Ruiz, Javier
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Wen, H. -P.
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Bose, Mrinal
Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture (TM) Technology-based SoC demonstrate about a 100x speedup on the emulator vis-a-vis the simulator.
Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step
(2013-01-01)
Chang, Chia-Ling (Lynn)
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Wen, Charles H. -P
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Bhadra, Jayanta
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電機工程學系
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Department of Electrical and Computer Engineering
Along with the shrinking CMOS process and rapid design scaling, both Iddq values and their variation of chips increase. As a result, the defect leakages become less significant when compared to the full-chip currents, making them more in-distinguishable for traditional Iddq diagnosis. Therefore, in this paper, a new approach called s-Iddq diagnosis is proposed for reinterpreting original data and diagnosing failing chips, intelligently. The overall flow consists of two key components, (1) s-Iddq transformation and (2) defect-syndrome matching: s-Iddq transformation first manifests defect leakages by excluding both the process-variation and design-scaling impacts. Later, defect-syndrome matching applies data mining with a pre-built library to identify types and locations of defects on the fly. Experimental results show that an average of 93.68% accuracy with a resolution of 1.75 defect suspects can be achieved on ISCAS'89 and IWLS'05 benchmark circuits using a 45nm technology, demonstrating the effectiveness of s-Iddq diagnosis.
Speeding up Bounded Sequential Equivalence Checking with Cross-Timeframe State-Pair Constraints from Data Learning
(2009)
Chang, Chia-Ling(Lynn)
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Wen, Charles H. -P.
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Bhadra, Jayanta
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A learning-and-filtering algorithm is proposed to uncover cross-timeframe state-pair constraints for speeding up SAT solving of bounded sequential equivalence checking (BSEC) problems. First, relaxed Boolean functions for flip-flop states at respective timeframes are learned from a small number of simulation data to derive the initial set of the state-pair candidates. Next, each candidate is examined and removed if both values in such a candidate have coordinately appeared during the simulation. Then, the validity of the remaining candidates is checked against the corresponding augmented circuit. Last, only the true constraints are annotated to the BSEC problems to facilitate SAT solving All benchmark circuits are synthesized under 10 configurations to produce different BSEC problems. Experimental results show that the new SAT solving runs 2-order faster in average compared to using MiniSAT 2.0 only Moreover, given a time bound, the total number of timeframes can increase by 8X-20X on 4 larger circuits after applying the proposed framework.