Browsing by Author "CHEN, MC"

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A CONTROLLED RADIATION SOURCE AND ELECTRON X-RAY FLUX RATIOS IN AN ELECTRON-BEAM METAL EVAPORATOR
(1988-07-01)
BHATTACHARYA, PK
;
REISMAN, A
;
CHEN, MC
;
交大名義發表
;
National Chiao Tung University
A NOVEL PROCESS FOR HIGH-PERFORMANCE SCHOTTKY-BARRIER PMOS
(1988-03-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A NOVEL PROCESS FOR HIGH-PERFORMANCE SCHOTTKY-BARRIER PMOS
(1989-05-01)
TSUI, BY
;
CHEN, MC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
AN EFFICIENT PRECLEAN OF ALUMINIZED SILICON SUBSTRATE FOR CHEMICAL-VAPOR-DEPOSITION OF SUBMICRON TUNGSTEN PLUGS
(1995-10-01)
YEH, WK
;
TSAI, MH
;
CHEN, SH
;
CHEN, MC
;
WANG, PJ
Preclean of aluminum trench and via patterned substrates is vital for successful selective chemical vapor deposition of tungsten (CVD-W). A convenient preclean method uses in situ. BCl3 plasma etching to remove the native metal oxide prior to conducting the CVD-W. During the plasma etching, however, the outsputtered aluminum oxide and aluminum can be redeposited on the sidewall of the trench and via hole and on the surface of the dielectric layer, where W nucleation is induced, resulting in creep-up and selectivity loss during tungsten deposition. By using a solution of hydroxylamine sulfate to pretreat the aluminum trench and via hole patterned substrates, we successfully avoid the creep-up and selectivity loss of W deposition.
AN EFFICIENT PRECLEAN OF ALUMINIZED SILICON SUBSTRATE FOR CHEMICAL-VAPOR-DEPOSITION OF SUBMICRON TUNGSTEN PLUGS
(1995-10-01)
YEH, WK
;
TSAI, MH
;
CHEN, SH
;
CHEN, MC
;
WANG, PJ
Preclean of aluminum trench and via patterned substrates is vital for successful selective chemical vapor deposition of tungsten (CVD-W). A convenient preclean method uses in situ. BCl3 plasma etching to remove the native metal oxide prior to conducting the CVD-W. During the plasma etching, however, the outsputtered aluminum oxide and aluminum can be redeposited on the sidewall of the trench and via hole and on the surface of the dielectric layer, where W nucleation is induced, resulting in creep-up and selectivity loss during tungsten deposition. By using a solution of hydroxylamine sulfate to pretreat the aluminum trench and via hole patterned substrates, we successfully avoid the creep-up and selectivity loss of W deposition.
BOLOMETRIC YBA2CU3O7-X INFRARED DETECTOR
(1991-09-12)
TSENG, TY
;
CHANG, CY
;
HAUNG, CJ
;
CHEN, MC
;
電子工程學系及電子研究所
Results of the measurement of optical detection in YBa2Cu3O7-x superconducting epitaxial films at a wavelength of 0.94-mu-m are presented. These films show bolometric responses at temperatures in the resistive transition regions which are strongly dependent on the bias current. For 0.94-mu-m radiation, electronically chopped at 20 Hz, measurement of a meander bridge yields a bolometric responsivity of approximately 6.1 V/W.
CONTACT RESISTIVITY OF SHALLOW JUNCTIONS FORMED BY IMPLANTATION THROUGH PT OR PTSI
(1992-09-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The specific contact resistance (rho(c)) of PtSi/p+ and PtSi/n+ contacts formed by ion implantation through Pt or PtSi was studied. A simple process to form self-aligned six-terminal Kelvin structure was developed in order to measure the specific contact resistance. For the PtSi/p+ contact system, a rho(c) lower than 1 x 10(-6) OMEGA-cm2 was achieved by BF2+ implantation at 40 keV to a dose of 5 x 10(15) cm-2. Increase of dose or energy could further decrease the rho(c) to be lower than 5 x 10(-7) OMEGA-cm2. The rho(c) of the PtSi/n+ contact system was lower than that of the PtSi/p+ contact system and a rho(c) of 1 x 10(-7) OMEGA-cm2 was obtained. These results indicate that although the PtSi-contacted junction is formed at temperatures lower than 800-degrees-C, the rho(c) is low enough to satisfy the requirements of submicrometer technology. We suggest that PtSi should be a favorable material to form shallow junctions and contacts simultaneously for future VLSI processes and to satisfy low thermal budget requirement.
COPPER CHEMICAL-VAPOR-DEPOSITION FROM CU(HEXAFLUOROACETYLACETONATE)TRIMETHYLVINYLSILANE
(1994-04-01)
CHIOU, JC
;
CHEN, YJ
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Copper chemical vapor deposition using Cu-hexafluoroacetylacetonate (hfac) trimethylvinylsilane (TMVS) as precursor was performed in a cold-wall low pressure chemical vapor deposition (CVD) reactor. The design and operation of the reactor are described. Copper deposition on thermal SiO2, W, and CoSi2 substrate surfaces was investigated over the temperature range of 160-300-degrees-C and pressure range of 10-1000 mTorr. The activation energies of Cu CVD were determined to be 13.33 and 11.54 kcal/mole for the W and CoSi2 substrates, respectively. The dependence of film resistivity, grain size, and growth rate on deposition pressure and temperature were also investigated. The film uniformity was found to be better than ten percent over a 4-inch diameter substrate. Experimental results also show that selective deposition can be achieved at a pressure of 10 mTorr within the temperature range of 160-200-degrees-C. In addition, hydrofluoric acid dipping was found to modify the SiO2 surface and influence the copper deposition on it.
DIELECTRIC DEGRADATION OF PT/SIO2/SI STRUCTURES DURING THERMAL ANNEALING
(1993-04-01)
TSUI, BY
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Traditionally it was believed that platinum does not interact with silicon dioxide during thermal treatment in an N2 ambient. In this work, however, dielectric degradation of the Pt/SiO2/Si structure during thermal annealing was observed. The density of surface states at the SiO2/Si interface increases and the dielectric strength of the oxide decreases after annealing at temperatures higher than 600-degrees-C. Ion implantation through the Pt/SiO2 structure enhances the degradation. After removal of the Pt film, a second annealing can reduce the surface state density but the dielectric strength cannot be recovered. Although material analysis such as AES and SIMS shows no obvious differences between the fresh SiO2 and the degraded SiO2, electrical analyses indicate that thermal stress is responsible for the increase of the surface states while Pt dissolving in SiO2 is responsible for the decrease of the dielectric strength. Thus, the process sequence should be taken into consideration for practical application.
DIELECTRICS DEGRADATION OF ALPHA-SI/CO/SIO2/SI STRUCTURE DURING FURNACE ANNEALING
(1994-07-01)
CHEN, BS
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The dielectric properties, which are highlighted on electrical characteristics, of alpha-Si/CO/SiO2/Si Structure after thermal annealing have been studied. A one-step high temperature (greater-than-or-equal-to 700-degrees-C) annealing process is found to deteriorate considerably the characteristics of the masking oxide. The tetraethylorthosilicate oxide needs a high-temperature preanneal prior to the self-aligned silicided (SALICIDE) process in order to prevent crack and pit formation and severe electrical degradation during silicidation annealing. A two-step annealing process with the first annealing performed at 550-degrees-C for 30 min has proved to be a trustworthy salicide process without affecting the dielectric properties of masking oxide.
EFFECT OF FLUORINE INCORPORATION ON THE THERMAL-STABILITY OF PTSI/SI STRUCTURE
(1993-01-01)
TSUI, BY
;
TSAI, JY
;
WU, TS
;
CHEN, MC
;
交大名義發表
The effect of fluorine incorporation on PtSi/Si structure is studied systematically. It is observed that the fluorine incorporation from ion implantation improves the high-temperature stability of the PtSi/Si structure. The optimum implantation energy is determined to be the energy at which the maximum percentage of the as-implanted fluorine ion locates at the PtSi/Si interface region. The SIMS analysis shows that the fluorine atom piles up at the PtSi/Si interface. The XPS analysis indicates that the fluorine atoms at the PtSi/Si interface are bonded to the silicon atoms in a form of SiF2 or SiF3. A fluorine-buffer (FB) model is proposed to explain the effect of fluorine incorporation. It is postulated that the Si-F layer acts as a buffer layer to change the PtSi/Si interface energy and preserve the integrity of the silicide layer at high temperature. Fluorinated Schottky junctions are fabricated and the electrical characteristics show that the sustainable process temperature can be improved from 650-degrees-C for the unfluorinated Schottky junctions to higher than 800-degrees-C for the fluorinated Schottky junctions.
EFFECT OF LASER GETTERING SCHEME IN SILICON
(1984)
LIOU, JY
;
LIN, JM
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
EFFECT OF POLY-SI GETTERING SCHEME ON THE QUALITY OF SI EPITAXIAL FILM
(1981)
CHEN, MC
;
LEE, JY
;
WU, HJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ELECTRICAL AND MICROSTRUCTURAL CHARACTERISTICS OF TI CONTACTS ON (001)SI
(1993-08-15)
LIAUH, HR
;
CHEN, MC
;
CHEN, JF
;
CHEN, LJ
;
電子工程學系及電子研究所
An investigation of the electrical and microstructural characteristics of the Ti contact on silicon has been carried out. The presence of As in Ti/n+-Si samples was found to retard the formation of polycrystalline silicide (p-silicide) compared with that in Ti/p+-Si samples with BF2+ implantation. Amorphous interlayers (a-interlayers) were found to be present in both Ti/n-Si and Ti/p-Si samples annealed at temperatures of and lower than 450-degrees-C. Although the Schottky barrier heights (SBH's) vary for about 0.05-0.08 eV for samples annealed over a temperature range from room temperature to 900-degrees-C, SBH's at the a-interlayer/n-Si and a-interlayer/p-Si were measured to be about 0.52-0.54 and 0.59-0.57 eV, respectively. The specific contact resistance (p(c)) in the Ti/n+-Si system was measured to be the lowest with a value of 1.4 X 10(-7) OMEGA cm2 when the a interlayer is present. In Ti/p+-Si system, the minimum rho(c) is about 3 X 10(-7) OMEGA cm2. The variation in contact resistance with annealing temperature for both Ti/n+-Si and Ti/p+-Si samples is correlated to the change in dopant concentration beneath the contacts as well as microstructures. In the temperature regime where the a interlayer is in contact with the silicon substrate, the junction diode leakage current densities (J(leak's)) are considerably lower than those in samples annealed at higher temperatures. The J(leak) at - 6 V reverse bias is lower than 1 nA/cm2. The breakdown voltage is about 14 V (16 V) for the n+/p (p+/n) junction. The thickness of consumed Si is less in samples annealed at low temperature, and the a-interlayer/Si or p-silicide/Si interface is accordingly farther away from the junction as well as the end-of-range defects. The interface of p-silicide/Si is rougher than that of a-interlayer/Si. In addition, the roughness of the p-silicide/Si interface increases with annealing temperature. For both p+/n and n+/p junctions annealed at 900-degrees-C, rough p-silicide/Si interfaces are thought to lead to spiking and increase the leakage currents.
EVALUATION OF INSITU FORMED W-TI AND MOSI2 AS A DIFFUSION BARRIER TO AL FOR COSI2 SILICIDED CONTACT
(1993-05-01)
YANG, FM
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A simple metallization process to form a shallow CoSi2 silicided contact and W-Ti diffusion barrier simultaneously has been developed. The process starts with depositions of a Co-Ti alloy layer and an overlying W layer on silicon wafers using a dual e-beam evaporation system; this is followed by a single-step annealing treatment in a normal flowing-nitrogen furnace. On the other hand, bilayer self-aligned shallow MoSi2/CoSi2/Si silicided contact can be derived from the W/Co-Mo/Si system by a two-step annealing treatment performed in the same environment. I-V characteristics for silicided p+n diodes with the diffusion barriers formed in situ were measured after they had been finished with Al deposition and post-Al annealing at temperatures from 350 to 600-degrees-C in N2. For comparison, Al/CoSi2/p+n and Al/p+n structures were also investigated. It turns out that the integrity of Al/W-Ti/CoSi2/P+n and Al/MoSi2/COSi2/P+ n silicided contacts can be preserved up to 5 50 and 500-degrees-C, respectively, for a 20 min annealing, while that of Al/CoSi2/P+n can be kept only up to 450-degrees-C.
FORMATION AND CHARACTERIZATION OF A PTSI CONTACTED N+P SHALLOW JUNCTION
(1990-09-01)
TSUI, BY
;
CHEN, MC
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
FORMATION OF 0.1-MU-M N+ P JUNCTION BY AS+ IMPLANTATION THROUGH PT OR PTSI FILM
(1990-04-01)
TSUI, BY
;
CHEN, MC
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
FORMATION OF BILAYER SHALLOW MOSI2/COSI2 SALICIDE CONTACT USING W/CO-MO ALLOY METALLIZATION
(1992-04-01)
YANG, FM
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A very simple process to form a bilayer shallow MoSi2/CoSi2/Si silicided contact using W/Co54Mo46/Si bilayer alloy metallization has been developed. Two-step annealing in a conventional flowing-nitrogen furnace is employed. The first annealing is performed at a temperature of 500-600-degrees-C, with the W film passivating the underlying Co-Mo alloy layer from being oxidized and consuming some Co. A shallow contact is feasible by selectively etching away the remaining outer layer of the Mo-dominant Mo-Co alloy (or W-Co alloy) phase to deduct the metal source which would finally be transformed into silicides. Silicide lateral growth which is observed during the silicidation of Co on Si does not occur in the present system. This is presumably because the formation of CoSi2 is not preceded by Co2Si or CoSi due to the nonrich Co source in the Co-Mo alloy system. The second annealing performed at a higher temperature of 700-950-degrees-C is to further transform the CoSi2 and mixed-silicide layers obtained after the first annealing into separate layers of MoSi2 and CoSi2.
FORMATION OF COBALT SILICIDE UNDER A PASSIVATING FILM OF MOLYBDENUM OR TUNGSTEN
(1991-05-01)
YANG, FM
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A very simple and reproducible cobalt silicide process with Mo/Co or W/Co bilayer metallization to overcome the oxidizing liability of Co annealed in a normal flowing-nitrogen furnace has been developed. Cobalt is deposited on blank and patterned silicon wafers in an electron-beam evaporation system followed by Mo (or W) deposition without breaking the vacuum. The cobalt silicidation is carried out using a two-step annealing process. The first annealing is performed at a temperature ranging from 400 to 600-degrees-C, during which the role of the upper layer of Mo (or W) is to protect the underlying Co layer from being oxidized while not disturbing the cobalt's silicidation process. Perfect selective etching of Mo (or W) can be accomplished by a NH4OH + H2O2 + (2-3)H2O solution. The second annealing is performed at a higher temperature of 750-degrees-C to completely transform the CoSi obtained in the first annealing into CoSi2 and induce grain growth of CoSi2, thus lowering the resistivity. X-ray diffraction, Auger electron spectroscopy, scanning electron microscopy, and sheet resistance measurement are used to characterize the silicide phase and microstructure.
FORMATION OF COBALT-SILICIDED P+N JUNCTIONS USING IMPLANT THROUGH SILICIDE TECHNOLOGY
(1992-11-15)
CHEN, BS
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates electrical and material properties of cobalt silicided p+ n junctions fabricated using implant through silicide (ITS) technology. The annealing procedure was carried out in an open-tube furnace with flowing nitrogen. To prevent residual oxygen in the furnace from reacting with the cobalt, a passivating film of molybdenum was used during the initial stage of annealing. BF2+ ion implantation was employed for the p+ n junction formation. The ITS scheme and the subsequent annealing conditions were evaluated by analysis of the material properties and investigation of the electrical characteristics of the silicided junctions. During high-temperature annealing (greater-than-or-equal-to 900-degrees-C), Co silicide releases its high surface energy via silicon precipitation and film agglomeration. High-temperature stability of the Co silicide can be improved by BF2+ ion implantation, as indicated by the retardation of film agglomeration and decreased degradation of sheet resistance. Cobalt-silicided p+ n junction diodes with 0.1 mum junction depth measured from the silicide/silicon interface were fabricated at a 700-degrees-C annealing and shown to possess excellent electrical properties. The leakage current density measured at -5 V was 0.5 nA/cm2 and a forward ideality factor of 1.006 was obtained. It was found that Co silicide is suitable to serve as an energy barrier and dopant diffusion source for the ITS scheme at low-temperature annealing. For elevated temperatures (greater-than-or-equal-to 900-degrees-C), the use of cobalt silicide as a dopant diffusion source becomes impractical because the dopant evaporation and silicide agglomeration severely degrade junction performance. Nevertheless, the silicide layer can be used as an energy barrier and implantation damage basin for high-temperature processes. No evidence of the electrically activated trapping centers related to the cobalt atoms was observed with BF2+ implantation at energies up to 100 keV. Thus, there is no fundamental limitation prohibiting the formation of cobalt-silicided shallow junctions being fabricated using ITS technology.