Browsing by Author "CHEN, MJ"

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A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES
(1986-04-01)
CHEN, MJ
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WU, CY
;
交大名義發表
;
工學院
;
National Chiao Tung University
A NEW METHOD FOR COMPUTER-AIDED OPTIMIZATION OF SOLAR-CELL STRUCTURES
(1985)
CHEN, MJ
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WU, CY
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交大名義發表
;
電控工程研究所
;
National Chiao Tung University
A NEW STRUCTURE-ORIENTED MODEL FOR WELL RESISTANCE IN CMOS LATCHUP STRUCTURES
(1987-04-01)
CHEN, MJ
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SZE, SC
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CHEN, HH
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WU, CY
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交大名義發表
A SIMPLIFIED COMPUTER-ANALYSIS FOR NORMAL-WELL GUARD RING EFFICIENCY IN CMOS CIRCUITS
(1987-08-01)
CHEN, MJ
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WU, CY
;
交大名義發表
;
工學院
;
National Chiao Tung University
A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTION
(1985)
CHEN, MJ
;
WU, CY
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
A STUDY OF LATCH-UP HYSTERESIS IN N-WELL CMOS BY MEANS OF I-V-CHARACTERISTICS AND PHOTOEMISSION TECHNIQUES
(1993-04-01)
CHEN, MJ
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JENG, JK
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Characterization of latch-up by I-V characteristics as well as by the photoemission technique has been extensively performed on a specially-designed CMOS p-n-p-n structure, furnishing different contact combinations for producing the hysteresis phenomenon of latch-up I-V characteristics. Based on these results, we have concluded that the parasitic lateral resistance of the p+ emitter in the n-well is the dominant factor in the formation of the I-V hysteresis. One example in the simplest contact combination has been presented to demonstrate this conclusion. In this example of hysteresis of the latch-up I-V curve, two active latch-up paths have been located separately using the photoemission technique and thus the corresponding branches of I-V curve have been determined. One latch-up path corresponding to the lower I-V branch has been verified to have the lateral p+ emitter resistance in series. The value of such resistance has been extracted by experimentally reproducing the lower I-V curve and has been shown to agree closely with that obtained independently from the p+ emitter. The hysteresis phenomenon in the latch-up I-V characteristics has been found to disappear after decreasing critically or eliminating this resistance by making the remaining p+ emitter contacts partially or totally connected to the power supply. A latch-up equivalent circuit drawn from the experimental results have been proposed to reasonably interpret the anomalous observations.
AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UP
(1986-05-01)
CHEN, MJ
;
WU, CY
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交大名義發表
;
工學院
;
National Chiao Tung University
AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS
(1986-04-01)
CHEN, MJ
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WU, CY
;
交大名義發表
;
工學院
;
National Chiao Tung University
ANALYTICAL DESIGN FORMULATION FOR MINORITY-CARRIER WELL-TYPE GUARD RINGS IN CMOS CIRCUITS
(1993-06-01)
CHEN, MJ
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HUANG, CY
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TSENG, PN
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Minority carriers injected from an active emitter into the substrate and partially collected by the bottom well junction in an epitaxial CMOS structure are studied. Two-dimensional numerical simulation has revealed that the minority-carrier collection current along the bottom well junction is contributed primarily by two mechanisms: the first due to minority carriers injected into a layer between the upper collecting plate and the bottom reflecting plate; and the second due to those penetrating the high/low junction and then spreading out in the large, highly-doped bulk as in the nonepitaxial case. Based on this observation, a new analytic model for the minority-carrier escape current has been developed as a measure of well-type guard ring efficiency. This model, including a closed-form expression as function of epitaxial layer thickness, well junction depth and guard ring width, has been confirmed by experimental data as well as by two-dimensional numerical simulation. As predicted by the model, the measured escape current has been found to be dominated by the second mechanism for the case of well junction depth close to epitaxial layer thickness while the first mechanism has been identified to dominate the escape current measured from the structure having sufficient epitaxial layer thicknesses.
BASE CURRENT REVERSAL PHENOMENON IN A CMOS COMPATIBLE HIGH-GAIN N-P-N GATED LATERAL BIPOLAR-TRANSISTOR
(1995-02-01)
HUANG, TH
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CHEN, MJ
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電控工程研究所
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Institute of Electrical and Control Engineering
Base current reversal phenomenon is newly observed in a CMOS compatible high gain n-p-n gated lateral bipolar transistor. We attribute this phenomenon to avalanche generation as verified experimentally and by two-dimensional device simulation. Detailed investigation reveals that: i) the multiplication ratio increases exponentially with the collector voltage or equivalently the peak field at the surface collector corner; and ii) the multiplication ratio is independent of not only the low level base-emitter forward biases applied but also the base width of the transistors fabricated by the same process. Design guideline for suppression of the base current reversal has been established such as to fully realize the potential of the gated lateral bipolar transistors, i.e., a very high current gain of 11,600 can be maintained as long as the power supply voltage is less than the critical value of 1.78 V. On the other hand, new application directly employing this phenomenon has been suggested. Comparisons between the base current reversal phenomenon in the gated lateral bipolar transistor and that in the vertical bipolar transistor have also been performed and significant differences between the two have been drawn and have been adequately explained.
CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS
(1986-10-01)
CHEN, MJ
;
WU, CY
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交大名義發表
;
工學院
;
National Chiao Tung University
DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS
(1994-10-01)
HUANG, CY
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CHEN, MJ
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電子工程學系及電子研究所
;
電控工程研究所
;
Department of Electronics Engineering and Institute of Electronics
This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guideline has been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from guard ring.
EFFECT OF BACK-GATE BIAS ON TUNNELING LEAKAGE IN A GATED P+-N DIODE
(1991-05-01)
CHEN, MJ
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
;
Institute of Electrical and Control Engineering
On a thin-oxide gate-controlled p+-n diode, this work first exhibits experimentally not only the substrate-bias-dependent characteristics of the tunneling leakage current but also the tunneling leakage characteristics independent of the substrate bias. This observation can be reasonably explained by the nature of the modulation of the surface space-charge region over the heavily doped p+ region as well as over the n-type substrate. Based on this work, the original understanding of such tunneling leakage has been improved.
EMPIRICAL MODELING FOR GATE-CONTROLLED COLLECTOR CURRENT OF LATERAL BIPOLAR-TRANSISTORS IN AN N-MOSFET STRUCTURE
(1995-01-01)
HUANG, TH
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CHEN, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The I-V characteristics of a gated lateral bipolar transistor in an n-MOSFET structure have been measured. The measured collector current has exhibited two distinct components: (i) the gate-con trolled collector current due to the modulation of the surface space-charge region; and (ii) the pure lateral bipolar transistor collector current which is independent of the gate bias applied. These two components have been separated experimentally and have been reproduced by analytic model expressions. The work is useful not only for understanding the hybrid-mode operation but also for designing appropriately the gated lateral bipolar transistors.
FOWLER-NORDHEIM LIMITED BAND-TO-BAND TUNNELING (FNBB) FOR P-MOSFET GATE CURRENT IN A FLOATING BULK CONDITION
(1995-01-01)
CHAO, KC
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CHEN, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new mechanism of Fowler-Nordheim tunneling limited band-to-band tunneling (FNBB) has been identified to be responsible for the gate current measured from p-MOSFETs with the bulk (n-well) floated. This mechanism has been found to occur in the gate-to-drain overlap region. Two-dimensional device simulations have successfully reproduced this gate current and thus the physical parameter values of the band-to-band tunneling model have been obtained.
GATE AND DRAIN CURRENTS IN OFF-STATE BURIED-TYPE P-CHANNEL LDD MOSFETS
(1992-12-01)
CHEN, MJ
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CHAO, KC
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HUANG, TH
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TSAUR, JM
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電控工程研究所
The buried-type p-channel LDD MOSFET's biased at high positive gate voltage exhibit new characteristics: 1) the ratio of the drain to gate currents is about 1 X 10(-3) to 5 X 10(-3); and 2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n+ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n+ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, not only the oxide field but also the gate and drain currents are independent of drain voltage.
NEW OBSERVATION AND THE MODELING OF GATE AND DRAIN CURRENTS IN OFF-STATE P-MOSFETS
(1994-05-01)
CHEN, MJ
;
CHAO, KC
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CHEN, CH
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide. At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current.
NEW OBSERVATION OF CHARGE INJECTION IN MOS ANALOG SWITCHES
(1994-02-03)
CHEN, MJ
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GU, YB
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WU, T
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HSU, PC
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LIU, TH
Based on experimental analogue MOS switches, the Letter reports a new observation of the charge injection component due to channel charges in weak inversion. As identified by the mixed-mode circuit and device simulations, this new component can contribute comparably to the switch-induced error voltage on a switched capacitor.
NEW OBSERVATION OF GATE CURRENT IN OFF-STATE MOSFET
(1991-09-01)
CHEN, MJ
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
;
Department of Electronics Engineering and Institute of Electronics
For a gate-controlled p+-n diode having gate-p+ overlap area of 3.7 x 10(-4) cm2, the work reports a new observation of the leakage current through a 235-angstrom gate oxide: the gate current components both due to Fowler-Nordheim electron tunneling through the gate-p+ overlap oxide and due to hot-electron injection have been separately detected. The corresponding gate current has been found to be dominated by Fowler-Nordheim electron tunneling prior to significant surface avalanche impact ionization. This observation is important for device application and for reliability study.
PREVENTIVE STRUCTURAL-ANALYSIS OF DATA-FLOW DIAGRAMS
(1992-02-01)
CHEN, MJ
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CHUNG, CG
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交大名義發表
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資訊科學與工程研究所
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National Chiao Tung University
Editors for dataflow diagrams (DFDs) perform structural analysis conventionally after structural errors have been introduced into DFDs. This is a corrective approach to eliminating structural errors. However, cross-examining voluminous DFDs to fix structural errors is time-consuming and frustrating. The paper proposes a preventive approach to structural analysis. The approach associates structural checking with editing operators so that editing operations that will introduce structural errors into DFDs are inhibited. As not all of the structural errors can be prevented, a decision on which structural errors can/should be prevented must be made. Consideration of two factors is suggested: the characteristics of structural errors and the construction method(s) for DFDs. Both considerations are demonstrated. A set of editing operators that enforce the prevention is then proposed and specified.