Browsing by Author "Chan, DSH"

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A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivation
(2004-09-01)
Wu, N
;
Zhang, QC
;
Zhu, CX
;
Chan, DSH
;
Du, AY
In this letter, we demonstrate a novel surface passivation process for HfO2 Ge pMOSFETs using SiH4 surface annealing prior to HfO2 deposition. By using SiH4 passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO2 Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a similar to 140% higher peak mobility than that of the device with surface nitridation.
Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric
(2004-11-01)
Wu, N
;
Zhang, QC
;
Zhu, CX
;
Chan, DSH
;
Li, MF
An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The surface SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition. The electrical measurement shows that an equivalent oxide thickness of 13.5 Angstrom and a leakage current of 1.16x10(-5) A/cm(2) at 1 V gate bias was achieved for TaN/HfO2/Ge MOS capacitors with the SiH4 surface treatment. (C) 2004 American Institute of Physics.
Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate
(2004-05-10)
Wu, N
;
Zhang, QC
;
Zhu, CX
;
Yeo, CC
;
Whang, SJ
Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 Angstrom and a leakage current of 5.02x10(-5) A/cm(2) at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (similar to400 degreesC) used in the chemical-vapor deposition process. (C) 2004 American Institute of Physics.
High-performance MIM capacitor using ALD high-k HfO2-Al2O3 laminate dielectrics
(2003-12-01)
Ding, SJ
;
Hu, H
;
Lim, HF
;
Kim, SJ
;
Yu, XF
For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO2-Al2O3 laminate dielectric' using atomic im layer deposition (ALD) technique. Our data indicates that the laminate NUM capacitor can provide high capacitance density of 12.8 fF/ mum(2) from 10 kHz up to 20 GHz, very low leakage current of 3.2 x 10(-8) A/cm(2) at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic. one of 1830 PPM/V-2, temperature coefficient of capacitance of 182 ppm/degreesC, and high breakdown field of similar to6 MV/cm as well as promising reliability. As a result, the HfO2-Al2O3 laminate is a very promising candidate for next generation MINI capacitor for radio frequency and mixed signal integrated circuit applications.
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode
(2004-10-01)
Zhu, SY
;
Yu, HY
;
Chen, JD
;
Whang, SJ
;
Chen, JH
Both P- and N-channel MOSFET's with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420degreesC. PMOSFETs with PtSi S/D show excellent electrical performance of an I-on/I-off similar to 10(7)-10(8) and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have similar to3 orders of magnitude larger I-off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I-on/I-off similar to 10(5) at low drain voltage. It can be attributed to the relatively higher barrier height (Phi(n)) of DySi2-x/n-Si than that of PtSi/p-Si (Phi(p)) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (similar to1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. (C) 2004 Published by Elsevier Ltd.
RF, DC, and reliability characteristics of ALD HfO2-Al2O3 laminate MIM capacitors for Si RF IC applications
(2004-06-01)
Ding, SJ
;
Hu, H
;
Zhu, CX
;
Kim, SJ
;
Yu, XF
High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO2-Al2O3 laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF/mum(2)) up to 20 GHz, low leakage current of 4.9 x 10(-8) A/cm(2) at 2 V and 125 degreesC, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (alpha) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.
Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode
(2004-05-01)
Zhu, SY
;
Yu, HY
;
Whang, SJ
;
Chen, JH
;
Shen, C
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.