Browsing by Author "Chang"

Now showing 1 - 20 of 33

Apparatus of multi-stage network for iterative decoding and method thereof
(2010-05-25)
Wong
;
Cheng-Chi
;
Lee
;
Yung-Yu
;
Lai
An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention.
Butterfly match-line structure and search method implemented thereby
(2011-03-08)
Huang
;
Po-Tsang
;
Hwang
;
Wei
;
Chang
The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.
Capacity-based compressed mode control method for inter-system handover in universal mobile telecommunication system
(2010-09-14)
Huang
;
Ching Yao
;
Chang
;
Cheng Ta
;
Ho
The Inter-System handover is one of the key features in the third generation cellular systems. The compressed mode, with variable transmission gaps and power levels, is standardized to support the inter-frequency system handover. To minimize the use of system resources while maintaining the border-cell handover quality, a capacity-based compressed mode control method of the present invention is proposed. Considering the tradeoff between the capacity and the communication quality, the control method can adaptively manage the compressed mode operation based on the potential impacts on the capacity and the effectiveness of the compressed mode measurement. The present invention will improve the effectiveness and performance of the compressed mode operation.
Copper metalized ohmic contact electrode of compound device
(2008-05-06)
Lee
;
Cheng-Shih
;
Chang
;
Edward Yi
;
Chen
The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.
Cu-metalized compound semiconductor device
(2008-09-02)
Chang
;
Edward Yi
;
Chang
;
Shang-Wen
;
Lee
The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.
Dual bandpass filter having serial configuration of coupled-line filters
(2009-03-31)
Chung
;
Shyh-Jong
;
Lin
;
Ke-Chiang
;
Chang
Two second-order bandpass filter are connected serially to obtain a dual bandpass filter. One is inductive and the other is capacitive. One has a low passband and the other has a high passband. Between them, a finite transmission zero is formed to suppress noise. The present invention achieves a passband as wide as 1 gigahertz so that it can be applied to a wireless local network, communication equipments and electronic devices.
Growth of GaAs epitaxial layers on Si substrate by using a novel GeSi buffer layer
(2007-08-21)
Chang
;
Edward Y.
;
Luo
;
Guangli
;
Yang
This invention provides a process for growing Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaxial layers by using metal organic chemical vapor deposition (MOCVD).The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaxial layer, such as Si0.1Ge0.9in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si01.Ge0.9due to the large mismatch between this layer and Si substrate.Furthermore, a subsequent 0.8 μm Si0.05Ge0.95layer, and/or optionally a further 0.8 μm Si0.02Ge0.98layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaxial layers.Finally, a GaAs epitaxial layer is grown on said Ge film by using MOCVD.
Integration structure of semiconductor circuit and microprobe sensing elements and method for fabricating the same
(2011-01-25)
Chiou
;
Jin-Chern
;
Chang
;
Chih-Wei
The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is etched to form a microprobe structure for detect physiological signals. Next, a deposition method is used to sequentially form an electrical isolated layer and an electrical conductive layer on the microprobes. Then, an electrical conductive material is used to electrically connect the electrical conductive layer with the electrical pads of the semiconductor circuit. Thus is achieved the integration of a semiconductor circuit and microprobe sensing elements in an identical semiconductor substrate with the problem of electric electrical isolated being solved simultaneously. Thereby, the voltage level detected by the microprobes will not interfere with the operation of the semiconductor circuit.
Interconnect of group III-V semiconductor device and fabrication method for making the same
(2010-12-07)
Lee
;
Cheng-Shih
;
Chang
;
Edward Yi
;
Chang
An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the first adhesion layer/diffusion barrier layer/second adhesion layer is located between the copper wire line and the group III-V semiconductor device, the adhesion between the diffusion barrier layer and other materials is improved. Therefore, the yield of the device is increased.
Manufacturing method of thin film transistor
(2006-01-31)
Chang
;
Kow Ming
;
Chung
;
Yuan Hung
A method of manufacturing a thin film transistor for solving the drawbacks of the prior arts is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.
Method and apparatus for self-compensation on belief-propagation algorithm
(2009-12-08)
Liao
;
Yen-Chin
;
Lin
;
Chien-Ching
;
Chang
A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.
Method and apparatus for switching data in communication system
(2010-05-25)
Lee
;
Chen-Yi
;
Liu
;
Chih-Hao
;
Lin
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Method and apparatus for switching data in communication system
(2010-05-25)
Lee
;
Chen-Yi
;
Lu
;
Jr-Hau
;
Lin
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive the source data possessing in a real coding dimension and covert it to converted the data possessing in a tolerable coding dimension; the judgment bits are set in the converted data to designate the data as source data or not. Later on, shifter circuit is used to shift the converted data in certain amount and generates a shifted data; meanwhile, the right side and left side of shifted data are used to start acquiring the real coding dimension to be used respectively as a first data and a second data. Finally, a comparison and selection circuit is used to compare the corresponding judgment bits in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Method and apparatus for telephone routing between PTN and PSTN
(2009-12-01)
Chang
;
Ming-Feng
;
Lin
;
Yi-Bing
;
Liang
Disclosed is a method and apparatus applicable to an interface between PSTN and PTN for telephone routing. The interface includes a branch switch, a key system, a network branch switch, and media gateway, etc. The telephone routing method and apparatus of the present invention creates, maintains, and utilizes a call-back routing table to enable a specified PSTN user to call the callback external leased line to reach a specified PTN user in a one-stage dialing manner. The process of one-stage dialing includes PTN call origination to PSTN, PSTN call origination to PTN, and callback tag insertion in the call-back routing table. The call-back routing table consists of a plurality of call-back tags. Each call-back tag consists of at least a data triple, i.e. PTN user identifier, PSTN called party telephone number, and callback leased line identifier.
Method for calculating syndrome polynomial in decoding error correction codes
(2005-10-11)
Lee
;
Chen-Yi
;
Chang
;
Hsie-Chia
;
Lin
The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.
Method for eliminating crosstalk in a metal programmable read only memory
(2007-10-30)
Chang
;
Meng-Fan
;
Wen
;
Kuei-Ann
The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, and a plurality of clamp transistors. When one of the bit lines is selected, bit lines adjacent to the selected bit line are fixed to a voltage value (VDD, GND or other voltages) by the clamp transistors. The clamping method can not cause voltage drops to the adjacent bit lines, and the crosstalk on the selected bit line can be eliminated simultaneously, so that the problem of read failures caused by the crosstalk in the high-speed metal programmable read only memory can be solved, and a higher speed can be reached.
Method for fabricating microneedle array and method for fabricating embossing mold of microneedle array
(2008-09-30)
Chiou
;
Jin-Chern
;
Hung
;
Chen-Chun
;
Chang
The present invention discloses a method for fast fabricating microneedle arrays with an embossing process and a method for fabricating an embossing mold of a microneedle array, wherein a master pattern of a high aspect ratio silicon microneedle array is fabricated with a microelectromechanical technology, and the master pattern is used to fabricate an embossing mold; a thermosetting material is filled into the embossing mold; then, baking, pressing and mold-stripping are undertaken; thereby, disposable solid polymer microneedle arrays can be batch-fabricated.
Method for fabricating nanometer gate in semiconductor device using thermally reflowed resist technology
(2005-09-13)
Chang
;
Edward Y.
;
Lee
;
Huang-Ming
The invention relates to a method for fabricating nanometer gate semiconductor device using thermally reflowed photoresist technology, comprising steps of (i) spin-coating two layers of photoresists on a substrate, where a bottom layer of photoresist is a polymeric photoresist having a lower sensitivity and a higher resolution, and a top layer of photoresist, is another polymeric photoresist having a higher sensitivity and a lower resolution, with respect to the electron beam; (ii) heating the photoresists for curing by way of using a hotplate; (iii) using photolithography in an electron beam direct writing manner to expose a pattern on the photoresists for forming a gate; (iv) using a developer and an etchant for developing and etching to form a recess on the gate; (v) plating a metallic layer on the recess of the gate using an electron gun evaporation technique; and (vi) removing the photoresists to obtain the gate, characterized in that after the etching of the recess of the gate, the photoresists are reflowed by using a hot plate heating manner within a predetermined period of time and temperature, such that the recess of the gate is formed with a nanometer-sized width.
Method for forming a semiconductor structure having nanometer line-width
(2009-03-10)
Chen
;
Szu-Hung
;
Lien
;
Yi-Chung
;
Chang
A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed.
Method for power-efficient transmission supporting integrated services over wireless local area network
(2010-01-26)
Shih
;
Chih-Yung
;
Cheng
;
Ray-Guang
;
Chang
This invention provides a method for power-efficient transmission supporting integrated service over WLAN. The said invention combines the polling-based and the contention-based mechanisms, named on-demand polling (ODP). In the ODP scheme, a voice station is in the polling list when it is in the active mode. During the idle mode, it is configured to operate in the sleep mode for saving power. Also, it adopts the contention-based mechanism to join the list again while returning from the idle mode. On the other hand, the data station adopts the contention-based mechanism to transmit its packets over WLAN. In addition, to achieve service differentiation, the said invention also employs a prioritized access probability for voice over data services. Simulation results show that the said invention can reduce the power consumption for voice stations and enhance the throughput for data stations.