Browsing by Author "Chang, HH"

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A 256 mA 0.72 V ground bounce output driver
(2000-05-01)
Yu, PC
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Chang, HH
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new output driver design called modified asymmetrical slew rate (MASR) output driver was proposed to reduce the simultaneous switching noise without sacrificing switching speed, for high speed and heavy loading applications. The driving capability of the output driver was designed to sink/source 64mA current @ V-OL/V-OH = 0.4V/4.6V, with 66pF and 50 Omega loading. When four drivers switch simultaneously, the ground bounce was design to be less than 0.8 V. The performances of the conventional, controlled slew rate (CSR), and MASR output drivers were analyzed by computer simulation. These three types of drivers were implemented with a 0.8 mu m CMOS process. The measured ground bounce of the conventional driver is 1.22 V, while the ground bounce of the MASR driver is reduced to 0.72 V. The propagation delays of the conventional and MASR drivers are the same. The performance of the MASR driver is better than that of the CSR driver in all aspects.
A 723-MHz 17.2-mW CMOS programmable counter
(1998-10-01)
Chang, HH
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Wu, JC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW.
A 723-MHz 17.2-mW CMOS programmable counter
(1998-10-01)
Chang, HH
;
Wu, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW.
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
(1997-01-01)
Ker, MD
;
Chang, HH
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding an extra ESD-implant mask, Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress, The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor, Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS IC's can be fully protected against ESD damage, Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
(2000-03-01)
Ker, MD
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered by noise pulses when the ICs are operated in the application systems. A cascoded design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latchup danger. The temperature dependence on the holding voltage of the cascoded LVTSCRs has been investigated in detail. From the experimental verification, the cascoded LVTSCRs can be fully turned on within a time below 20 ns. The ESD robustness per layout area of the three-cascoded LVTSCRs can be 0.83 V/mu m(2) in a 0.35-mu m silicide CMOS process without using the extra silicide-blocking and ESD-implant masks, whereas the ESD robustness of the gate-grounded NMOS is only 0.25 V/mu m(2). Such cascoded LVTSCRs with a tunable holding voltage greater than VDD can provide CMOS ICs with effective component-level ESD protection but without causing catchup danger if it is accidentally triggered by the system-level overshooting or undershooting noise pulses. (C) 2000 Elsevier Science Ltd. All rights reserved.
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
(1996-04-01)
Ker, MD
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines, The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid the unexpected ESD damages on internal circuits, Experimental results show that it can perform excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit, The device characteristics under high-temperature environment of up to 150 degrees C is also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications
(2000)
Ker, MD
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Chen, TY
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Wu, CY
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Chang, HH
;
電子工程學系及電子研究所
An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the HEM (MM) ESD level of up to 6kV (400V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond pad capacitance) for high-frequency applications.
Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
(1999-02-01)
Chang, HH
;
Ker, MD
;
Wu, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-mu m bulk CMOS process. (C) 1998 Elsevier Science Ltd. All rights reserved.
Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's
(1995)
Ker, MD
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Wu, CY
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Cheng, T
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Chang, HH
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Wu, MJN
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
(2000-08-01)
Ker, MD
;
Chen, TY
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond-pad capacitance) for high-frequency applications.
Improved output ESD protection by dynamic gate floating design
(1998-09-01)
Chang, HH
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A dynamic gate Boating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-mu m CMOS process.
New diode string design with very low leakage current for using in power supply ESD clamp circuits
(2000)
Ker, MD
;
Lo, WY
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Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5-V (3.3-V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125 degrees C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve the whole-chip ESD protection scheme.
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
(1999-03-01)
Ker, MD
;
Chen, TY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout. (C) 1999 Elsevier Science Ltd. All rights reserved.
Optimization of parameter design: an intelligent approach using neural network and simulated annealing
(2000-12-01)
Su, CT
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Chang, HH
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工業工程與管理學系
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Department of Industrial Engineering and Management
Parameter design optimization problems have found extensive industrial applications, including product development, process design and operational condition setting. The parameter design optimization problems are complex because non-lineal relationships and interactions may occur among parameters. To resolve such problems, engineers commonly employ the Taguchi method. However, the Taguchi method has some limitations in practice. Therefore, in this work, we present a novel means of improving the effectiveness of the optimization of parameter design. The proposed approach employs the neural network and simulated annealing, and consists of two phases. Phase I formulates an objective function for a problem using a neural network method to predict the value of the response for a given parameter setting. Phase 2 applies the simulated annealing algorithm to search for the optimal parameter combination. A numerical example demonstrates the effectiveness of the proposed approach.
Parameter design optimization via neural network and genetic algorithm
(2000-09-01)
Su, CT
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Chiu, CC
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Chang, HH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
Among the many extensive industrial applications which parameter design optimization problems have found include product development, process design and operational condition settings. The parameter design optimization problems are complex owing to that nonlinear relationships and interactions may occur among parameters. To resolve such problems, engineers commonly employ the Taguchi method. However, the Taguchi method has some limitations in practice. Therefore, in this work, we present a novel means of improving the effectiveness of the optimization of parameter design. The proposed approach employs the neural network and generic algorithm, and consists of two phases. Phase 1 formulates a fitness function for a problem by a neural network method to predict the value of the response for a given parameter setting. Phase 2 applies a genetic algorithm to search for the optimal parameter combination. A numerical example demonstrates the effectiveness of the proposed approach. Significance: This work provides an efficient approach to optimize the parameter design problems, which is relatively simple and is fairly easy for engineers to apply to diverse industrial applications.
Topology-aided cross-layer fast handoff designs for IEEE 802.11/Mobile IP environments
(2005-12-01)
Tseng, CC
;
Yen, LH
;
Chang, HH
;
Hsu, KC
;
交大名義發表
This study first reviews state-of-the-art fast handoff techniques for IEEE 802.11 or Mobile IP networks. Based on that review, topology-aided cross-layer fast handoff designs are proposed for Mobile IP over IEEE 802.11 networks. Time-sensitive applications, such as voice over IP (VoIP), cannot tolerate the long layer-2. plus layer-3 handoff delays that arise in IEEE 802.11/Mobile IP environments. Cross-layer designs are increasingly adopted to shorten the handoff latency time. Handoff-related layer-2 triggers may reduce the delay between layer-2 handoff completion and the associated layer-3 handoff activation. Cross-layer topology information, such as the association between 802.11 access points and Mobile IP mobility agents, together with layer-2 triggers, can be utilized by a mobile node to start layer-3 handoff-related activities, such as agent discovery, address configuration, and registration, in parallel with or prior to those of layer-2 handoff. Experimental results indicate that the whole handoff delay can meet the delay requirement of VoIP applications when layer-3 handoff activities occur prior to layer-2 handoffs.