ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

Abstract

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond-pad capacitance) for high-frequency applications.