Browsing by Author "Chang, Han-Tung"

Now showing 1 - 7 of 7

Device Simulation of P-InAlN-Gate AlGaN/GaN High Electron Mobility Transistor
(2014-01-01)
Shrestha, Niraj Man
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Lin, Yueh-Chin
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Chang, Han-Tung
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Li, Yiming
;
Chang, Edward Yi
Enhancement mode AlGaN/GaN high electron mobility transistor with p-InAlN gate is designed and successfully studied its electrical properties. Threshold voltage of the device is 1.9 V, which is required magnitude of threshold voltage for real device. Similarly, the maximum drain current is 520 mA/mm and trasconductance is 183 mS/mm, which is the record estimation for enhancement-mode (e-mode) device with recorded threshold voltage. P-InAlN layer injects hole to the barrier at higher gate voltage and results in comparatively larger drain current. Selective area etching and re-grow AlInN causes thin barrier layer beneath the gate. This recess like p-InAlN structure can reduce the concentration of 2DEG; and thus results the high magnitude of threshold voltage.
On Characteristic Variability of 16-nm-Gate Bulk FinFET Devices Induced by Intrinsic Parameter Fluctuation and Process Variation Effect
(2013-01-01)
Chen, Chieh-Yang
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Li, Yiming
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Chen, Yu-Yu
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Chang, Han-Tung
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Hsu, Sheng-Chia
On Statistical Variation of MOSFETs Induced by Random-Discrete-Dopants and Random-Interface-Traps
(2012)
Li, Yiming
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Su, Hsin-Wen
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Chen, Chieh-Yang
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Cheng, Hui-Wen
;
Chen, Yu-Yu
In this work, we statistically study characteristic fluctuation of 16-nm-gate high-kappa/metal gate (HKMG) MOSFETs by random-discrete-dopants (RDDs) inside silicon channel and random-interface-traps (RITs) at high-kappa/silicon interface. Randomly generated devices with three-dimensional (3D) RDDs inside device channel and 2D RITs at HfO2/Si interface are incorporated into quantum mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to RITs near the source and drain ends, and RDDs near the device channel surface and silicon substrate. Characteristic fluctuations are affected to different extents by the random combinatorial RDDs and RITs. Nonlinearly correlated RDDs and RITs further violate the statistical assumption of independent identical distributions between the RDDs- and RITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is less than their statistical sum due to local interaction of surface potentials resulting from the RDDs and RITs simultaneously. In contrast to RDDs fluctuation, the screening effect of device\'s inversion layer cannot effectively screen potential\'s variation resulting from RITs; thus, devices still have noticeable gate capacitance characteristic fluctuation under high gate bias.
Process Variation Effect, Metal-Gate Work-Function Fluctuation and Random Dopant Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFET Devices
(2015)
Li, Yiming
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Chang, Han-Tung
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Lai, Chun-Ning
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Chao, Pei-Jung
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Chen, Chieh-Yang
In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-kappa/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.
Random Work Function Induced DC Characteristic Fluctuation in 16-nm High-kappa/Metal Gate Bulk and SOI FinFETs
(2012)
Su, Hsin-Wen
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Chen, Yu-Yu
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Chen, Chieh-Yang
;
Cheng, Hui-Wen
;
Chang, Han-Tung
This work studies the metal gate\'s work function fluctuation induced DC characteristic fluctuation in the 16-nm bulk and silicon-on-insulator (SOI) fm-type field effect transistor (FinFET) devices using an experimentally calibrated 3D device simulation. The method of localized work function fluctuation simulation enables us to estimate local fluctuations including the nanosized grain\'s random effects of FinFET with TiN/HfO2 gate stacks. The result of this study shows characteristic fluctuation strongly depends upon the size of localized nanosized metal grains. The shape of grains does have marginal influence on device\'s variability.
Statistical Device Simulation of Characteristic Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFETs Induced by Various Discrete Random Dopants
(2016)
Sung, Wen-Li
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Chang, Han-Tung
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Chen, Chieh-Yang
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Chao, Pei-Jung
;
Li, Yiming
We study the impact of random dopant fluctuation (RDF) on electrical characteristics of 10-nm-gatehigh kappa/metal gate gate-all-around silicon nanowire MOSFET devices. To provide the best accuracy of device simulation, model parameters are validated by using full quantum mechanical simulation and calibrated with experimental results. Physical mechanism of RDs inside channel and penetration from the source/drain extensions into the channel is discussed. Electrical characteristic of the device is estimated with respect to different types of RDF.
Statistical Device Simulation of Intrinsic Parameter Fluctuation in 16-nm-Gate N- and P-type Bulk FinFETs
(2013-01-01)
Chen, Yu-Yu
;
Huang, Wen-Tsung
;
Hsu, Sheng-Chia
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Chang, Han-Tung
;
Chen, Chieh-Yang
In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-kappa / metal gate n- and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations\' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.