Browsing by Author "Chang, Jui-Chung"
Now showing 1 - 4 of 4
- Results Per Page
- Sort Options
Item type:Item, A Reliable Brain Computer Interface Implemented on an FPGA for a Mobile Dialing System(2014-01-01) ;Feng, Chih-Wei ;Hu, Ting-Kuei ;Chang, Jui-Chung ;Fang, Wai-Chi電子工程學系及電子研究所This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose a phone number by gazing at the display interface. This proposed EEG system has been implemented in Field-Programmable Gate Arrays (FPGA), and shows high accuracy, high integration density, and low cost. These features are meaningful for implementing a real-time SSVEP-based BCI.Item type:Item, A Reliable Brain Computer Interface Implemented On FPGA For Mobile Dialing System(2015) ;Feng, Chih-Wei ;Chang, Jui-Chung ;Chen, Wei-Chen ;Fang, Wai-Chi電子工程學系及電子研究所This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.Item type:Item, An Efficient ASIC Implementation of 16-channel On-line Recursive ICA Processor for Real-time EEG System(2014-01-01) ;Fang, Wai-Chi ;Huang, Kuan-Ju ;Chou, Chia-Ching ;Chang, Jui-ChungCauwenberghs, GertThis is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.Item type:Item, An Efficient VLSI Implementation of SVD Processor of On-line Recursive ICA for Real-time EEG System(2014-01-01) ;Fang, Wai-Chi ;Chang, Jui-Chung ;Huang, Kuan-Ju ;Feng, Chih-WeiChou, Chia-ChingThis paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.