Browsing by Author "Chang, T. C."

Now showing 1 - 20 of 24

Analysis of bump resistance and current distribution of ultra-fine-pitch microbumps
(2013-01-01)
Chang, Y. W.
;
Peng, H. Y.
;
Yang, R. W.
;
Chen, Chih
;
Chang, T. C.
To keep up with the demand of continuous increase in device densities, the integration of three-dimensional integrated circuits (3D-IC) has become the most probable solution, and the utilization of ultra-fine-pitch microbump has emerged as an essential component of 3D-IC technology. In this study, a Kelvin bump structure was fabricated and resistances measured at different angles on a 20.0 mu m microbump were investigated. The microbump resistance at 0 degrees, 60 degrees, 120 degrees, and 180 degrees are 74.7, 45.9, 14.6, and 13.7 m Omega, respectively. These high resistances in microbumps may result in high interconnect resistance and cause resistance/capacitance (RC) delay, and thus lower the electrical performance of 3D-IC. A series of finite-element-model (FEM) was built to analyze the distribution of electric field in microbump. The FEM results have shown that the current is distributed uniformly in the thin solder joint, but current crowding still occurs in the Cu under-bump-metallization (UBM). The finding of the current crowding in the Cu UBM is the main cause of high resistances in the microbump. Thickening the Al trace, for example, from 0.4 mu m to 1.5 mu m, is a direct solution to reduce the unexpected high microbump resistance. A numerical model which treated solder joints as a resistance network was also performed in this study. For comparison, both FEM and the numerical model show the same trend and agree with the measurement results from Kelvin bump structure. The results all point to one thing: thickening the Al trace turn out to be the most effective approach to reduce high microbump resistance. When the Al trace thickness is increased from 0.8 to 3.0 mu m, the microbump resistance is decreased to half of the original value, resulted from the alleviation of current crowding in the Cu UBM. (C) 2012 Elsevier Ltd. All rights reserved.
Analysis of parasitic resistance and channel sheet conductance of a-Si : H TFT under mechanical bending
(2007)
Wang, M. C.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Tsao, S. W.
;
Chen, J. R.
The effect of mechanical strain on the performance of a-Si: H thin-film transistors (TFTs) with different channel lengths was studied under uniaxial compressive and tensile strain applied parallel to the TFT source-drain current path. The source-drain parasitic resistance and channel sheet conductance were extracted to explain the device performance under mechanical strain. These results indicate that the compressive bending leads to a significant decrease (similar to 16%) in the source-drain parasitic resistance. The channel sheet conductance has shown a 6% variation under mechanical bending. The variation under mechanical bending strain originates from the evolution of defect state density in a-Si:H channel material. (c) 2007 The Electrochemical Society.
Effect of supercritical fluids on field emission from carbon nanotubes
(2006)
Liu, P. T.
;
Tsai, C. T.
;
Kin, K. T.
;
Chang, P. L.
;
Chen, C. M.
This paper proposes a novel method to enhance the emission characteristics of carbon nanotubes (CNTs). It is extremely possible for CNTs to adsorb moisture and other contaminants during the fabrication processes, leading to the degraded field emission characteristics. In this work, CNT emitters are activated with commonly used heating process and supercritical carbon dioxide (SCCO2) fluids technology for removing adsorbed residue moisture. Experimental results have demonstrated that the electrical stability and field emission enhancement of CNT emitters are effectively achieved by the SCCO2 fluids treatment compared to the heating process, due to the minimization of residuary moisture in CNTs.
Fast phase transformation due to electromigration of 18 mu m microbumps in three-dimensional integrated-circuit integration
(2014-12-15)
Chang, Y. W.
;
Chen, Chih
;
Chang, T. C.
;
Zhan, C. J.
;
Juang, J. Y.
The electromigration behavior was investigated in 18-mu m SnAg microbumps at 150 degrees C. The monitored resistance increase abruptly soon after the current stressing of 4.6 x 10(4) A/cm(2) was applied but the resistance rose much slower after a certain period of time. The formation of the high-resistivity Ni3Sn4 intermetallic compounds (IMCs) was responsible for the abrupt resistance increase in the beginning of the current stressing. The whole solder joint was transformed into an IMC joint. Because IMC has a higher electromigration resistance than the solder, a much slower increase in resistance was resulted after the solder joint was transformed into IMCs. (C) 2014 Elsevier B.V. All rights reserved.
High-density nano-pillar SiOx-based resistive switching memory using nano-sphere lithography to fabricate a one diode - one resistor (1D-1R) architecture
(2014-01-01)
Chang, Y. F.
;
Ji, L.
;
Chen, Y. C.
;
Zhou, F.
;
Tsai, T. M.
A highly compact, one diode - one resistor (1D-1R) nano-pillar device architecture has been demonstrated using nano-sphere lithography (NSL) to fabricate SiOx-based resistive switching (RS) memory. The intrinsic SiOx-based resistive switching element and Si-based PN diode are self-aligned on the epitaxial silicon wafer using NSL and a deep-Si-etch process without using conventional photolithography. The DC electrical performance, an AC pulse response in the 50 ns regime, capability for multi-bit operation, and high readout margin immunity for sneak path issue demonstrate good potential for high-speed nonvolatile memory (NVM). The NSL fabrication process is an efficient, economical approach to enable large-scale patterning of 1D-1R architectures while providing excellent NVM performance for future applications.
Implementation of Functionally Complete Boolean Logic and 8-bit Adder in CMOS Compatible 1T1R RRAMs for In-Memory Computing
(2018-01-01)
Wang, Z. R.
;
Li, Y.
;
Su, Y. T.
;
Zhou, Y. X.
;
Yin, K. S.
RRAM is a promising candidate to construct in-memory computing architecture which can break through the von Neumann bottleneck. Taking advantage of the CMOS compatible 1T1R RRAM, functionally complete Boolean logics can be realized within two steps in a single unit that can suppress sneak pass problem and avoid cascading problem partially. In addition, an 8-bit pre-calculation adder with low computation complexity is designed and demonstrated experimentally to verify the feasibility and efficiency of 1T1R based in-memory computing architecture, which is applicable to future energy-efficient information processing systems.
Mechanical bending effect on the photo leakage currents characteristic of amorphous silicon thin film transistors
(2010-11-01)
Wang, M. C.
;
Tsao, S. W.
;
Chang, T. C.
;
Lin, Y. P.
;
Liu, Po-Tsun
The photo leakage current (I(PLC)) characteristic of a-Si:H TFTs under different bending strains has been studied. The larger I(PLC) of a-Si:H TFTs under the outward bending strain is due to larger conductivity of a-Si:H, stemmed from the shift up of Fermi level (E(F)). Experimental results show the I(PLC) of a-Si:H TFTs under the outward bending strain is larger than that of flattened and inward bending a-Si:H TFTs in the density of states (DOS) limited region, stemmed from the lower recombination centers present in outward bending a-Si:H material. Furthermore, the extracted smaller activity energy (E(a)) of a-Si:H TFTs under the outward bending strain also confirmed the shift of E(F). (C) 2010 Elsevier Ltd. All rights reserved.
Mechanical bending effect on the photo leakage currents characteristic of amorphous silicon thin film transistors
(2010-11-01)
Wang, M. C.
;
Tsao, S. W.
;
Chang, T. C.
;
Lin, Y. P.
;
Liu, Po-Tsun
The photo leakage current (I(PLC)) characteristic of a-Si:H TFTs under different bending strains has been studied. The larger I(PLC) of a-Si:H TFTs under the outward bending strain is due to larger conductivity of a-Si:H, stemmed from the shift up of Fermi level (E(F)). Experimental results show the I(PLC) of a-Si:H TFTs under the outward bending strain is larger than that of flattened and inward bending a-Si:H TFTs in the density of states (DOS) limited region, stemmed from the lower recombination centers present in outward bending a-Si:H material. Furthermore, the extracted smaller activity energy (E(a)) of a-Si:H TFTs under the outward bending strain also confirmed the shift of E(F). (C) 2010 Elsevier Ltd. All rights reserved.
Memory characteristics of Co nanocrystal memory device with HfO(2) as blocking oxide
(2007-03-26)
Yang, F. M.
;
Chang, T. C.
;
Liu, P. T.
;
Yeh, P. H.
;
Yu, Y. C.
In this letter, the Co nanocrystals using SiO(2) and HfO(2) as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window was estimated to similar to 1 V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 10(6) write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry. (c) 2007 American Institute of Physics.
Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide
(2007-03-26)
Yang, F. M.
;
Chang, T. C.
;
Liu, P. T.
;
Yeh, P. H.
;
Yu, Y. C.
In this letter, the Co nanocrystals using SiO2 and HfO2 as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window was estimated to similar to 1 V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 10(6) write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry. (c) 2007 American Institute of Physics.
Metal nanocrystals as charge storage nodes for nonvolatile memory devices
(2007-02-10)
Yeh, P. H.
;
Chen, L. J.
;
Liu, P. T.
;
Wang, D. Y.
;
Chang, T. C.
The memory effects of the metal nanocrystals were found to be more pronounced than those of the semiconductor nanocrystals. Various metal nanocrystals as charge storage nodes are reviewed. The memory effects have strong relationship with the work function, and the work function can be modulated by changing the metal species. By tunneling dielectrics engineering, the optimum I-GWrite/Erase/I-G Retention ratio can be obtained. (c) 2006 Elsevier Ltd. All rights reserved.
n(+)-doped-layer-free microcrystalline silicon thin film transistors fabricated with the CuMg as source/drain metal
(2007-07-09)
Wang, M. C.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Xiao, R. W.
;
Lin, L. F.
The feasibility of using CuMg as source/drain metal electrodes for n(+)-doped-layer-free microcrystalline silicon thin film transistors (mu-Si:H TFTs) has been investigated. The Ohmic-contact characteristic has been achieved by using the CuMg alloy as source/drain metal. Furthermore, a wet etching process of Cu alloy source/drain metal has been completed by using the ferric chloride base etchant. The proposed mu-Si:H TFT has shown similar electrical characteristic with the mu-Si:H TFT with n(+)-doped layer. The experimental result also showed that the CuMg alloy was suitable for the replacement of n(+)-doped layer in thin film transistor liquid-crystal displays. (C) 2007 American Institute of Physics.
Nickel nanocrystals with HfO2 blocking oxide for nonvolatile memory application
(2007-05-28)
Yang, F. M.
;
Chang, T. C.
;
Liu, P. T.
;
Chen, U. S.
;
Yeh, P. H.
A distributed charge storage with Ni nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated in this study. The mean size and aerial density of the Ni nanocrystals are estimated to be about 5 nm and 3.9x10(12)/cm(2), respectively. The nonvolatile memory device with Ni nanocrystals exhibits 1 V threshold voltage shift under 4 V write operation. The device has a long retention time with a small charge lose rate. Besides, the endurance of the memory device is not degraded up to 10(6) write/erase cycles. (C) 2007 American Institute of Physics.
Nickel silicide nanocrystals embedded in SiO2 and HfO2 for nonvolatile memory application
(2007-12-03)
Yang, F. M.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Yeh, Y. H.
;
Yu, Y. C.
In this study, a nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated. A significant memory effect is observed during the characterization of the electrical properties. When a low operating voltage, 4 V, is applied, a significant threshold voltage shift of 1.3 V, is observed. The processing of this structure is compatible with the current manufacturing technology of semiconductor industry. (C) 2007 Published by Elsevier B.V.
Photo-leakage-current characteristic of F incorporated hydrogenated amorphous silicon thin film transistor
(2007-05-07)
Wang, M. C.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Tsao, S. W.
;
Chen, J. R.
The photo-leakage-current (I-PLC) characteristic of F incorporated a-Si:H thin film transistor (TFT) has been studied. The device activation energy (E-a) of a-Si:H(:F) TFTs is higher than those of typical a-Si:H TFTs, and resulted in the shift down of Fermi level in a-Si:H(:F). Experimental results show that the I-PLC of a-Si:H(:F) TFTs is smaller than that of conventional a-Si:H TFTs in the density of states limited region, stemmed from the higher recombination centers present in a-Si:H(:F) material. However, the higher I-PLC is observed in the hole conduction region, resulted from the larger E-a in the a-Si:H(:F) TFTs. (C) 2007 American Institute of Physics.
Schottky barrier height for the photo leakage current transformation of a-Si : H TFTs
(2007)
Wang, M. C.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Li, Y. Y.
;
Xiao, R. W.
For effectively reducing the off-state signal loss resulting from the a-Si: H thin film transistors' (TFTs) photo leakage current, the a-Si: H TFTs with the use of indium tin oxide as source-drain metal have been fabricated for this study. A remarkable transformation in photo leakage current has been observed under the 3300 cd/m(2) cold cathode fluorescent lamp (CCFL) backlight illumination. The source-drain barrier height engineering has been proposed for this study. According to the energy band diagram, the barrier height for hole is estimated to be about 3 eV. As a result, the photogeneration holes blocked in the Schottky barrier could effectively result in the different characteristic of photo leakage current. (c) 2007 The Electrochemical Society.
Source-drain barrier height engineering for suppressing the a-Si : H TFTs photo leakage current
(2007-12-03)
Wang, M. C.
;
Chang, T. C.
;
Liu, P. T.
;
Li, Y. Y.
;
Huang, F. S.
For effectively reducing the off-state signal loss resulted from the a-Si:H TFTs photo leakage current, the a-Si:H TFTs with the use of ITO as source-drain metal have been fabricated for this study. Several TFT structures have been fabricated to examine this characteristic. A remarkable reduction in photo leakage current has been observed under the 3300 cd/m(2) CCFL backlight illumination. The source-drain barrier height engineering has been proposed for these results. According to the energy band diagram, the barrier height for hole is estimated about 3 eV. As a result, the photo-generation holes blocked in the source-drain barrier height could effectively reduce the photo leakage current in off-state. (C) 2007 Elsevier B.V. All rights reserved.
Suppression of Schottky leakage current in island-in amorphous silicon thin film transistors with the Cu/CuMg as source/drain metal
(2007-08-06)
Wang, M. C.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Xiao, R. W.
;
Lin, L. F.
The feasibility of using Cu/CuMg as a source/drain metal for the island-in amorphous silicon thin film transistors (a-Si:H TFTs) has been investigated. The issue of adhesion between the Cu film and n(+)-a-Si layer has been overcome by introducing the Cu/CuMg alloy. Furthermore, the suppression of Schottky leakage current in metal/a-Si:H structure was also observed in the island-in a-Si:H TFT. The island-in a-Si:H TFT exhibited the mobility of 0.52 cm(2)/V s, the subthreshold slope of 0.78 V/decade, and the V-th of 3.02 V. The experimental result also showed superior performance of the a-Si:H TFT with minimal loss of critical dimension and good thermal stability.
The instability of a-Si : H TFT under mechanical strain with high frequency ac bias stress
(2007)
Wang, M. C.
;
Chang, T. C.
;
Liu, Po-Tsun
;
Tsao, S. W.
;
Lin, Y. P.
The instability of amorphous Si thin film transistors under uniaxial strain has been studied. Compared to the effect of tensile bias stress, larger threshold voltage shift is observed under compressive bias stress. These results are related to the damage of weak Si-Si bonds during the ac bias stress. However, the V-th shift of devices on the re-flattened substrate is larger after tensile strain than that of compressive strain. In addition, the defeat diminished effect of tensile situation is decreased after re-flattening the device. Therefore, after re-flattening the substrate the Vth shift resulting from tensile bias stress is larger than that of the compressive one. (c) 2007 The Electrochemical Society.
The Mechanisms of on/off currents for the Dual-Gate a-Si : H thin film transistors with various length sizes of indium-tin-oxide top gate
(2006-01-01)
Liang, Chung-Yu
;
Chang, T. C.
;
Po-Tsun, Liu
;
Gan, Feng-Yuan
;
Yeh, F. S.
Two types of dual-gate a-Si:H TFTs with four different sizes of transparent indium-tin-oxide (ITO) top gate length have been made for the static characteristics investigation. With various sizes of ITO top gate length, we clearly identify that the various on currents for the dual-gate TFTs with dual-gate driving are due to the high resistance of the parasitic intrinsic a-Si:H regions between the back electron channel and the source/drain contact. For the off state of the dual-gate TFTs, the Poole-Frenkel effect is also enhanced due to the back channel accumulation holes in the vicinity to the source/drain contact. Furthermore, we first observe that the dual-gate driving a-Si:H TFTs exhibit extremely low photo-leakage currents during a certain range of negative gate voltages under illumination. The high on-off current ratio under backside illumination makes the dual-gate TFTs the suitable devices as the switching elements in liquid crystal display (LCD) or other applications.