Browsing by Author "Chang, Tian Sheuan"

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A Multi-Bin Constant Throughput CABAC Decoder for HEVC
(2015)
Chen, Hsuan-Ku
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Fang, Chih-Chung
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate count (810Mbins/sec) when operating at 270MHz.
A Real Time 1080P 30FPS Gaussian Mixture Modeling Design for Background Subtraction And Object Extraction
(2014-01-01)
Hsu, Shuo-Wen
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The Gaussian Mixture Modeling (GMM) algorithm with connected component labeling as object extraction provide robust background subtraction but suffer from complexity, and large buffer or high bandwidth due to the frame level operations. For real time application needs, this paper proposed a block based GMM design for background subtraction with message passing between blocks to avoid performance drop. The corresponding parallel hardware design can reach real time 1080P@30fps and cost 164.82K gate-counts at 125MHz with 90nm process.
A Reconfigurable Inverse Transform Architecture Design for HEVC Decoder
(2013)
Chiang, Pai-Tse
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we present a reconfigurable hardware design which can support the inverse transform size from 4x4 to 32x32 in HEVC (High Efficiency Video Coding). We explore the coefficient properties of various inverse transforms such that a base inverse transform unit can be reconfigured or refined to generate other size of inverse transform. The implementation in 90nm technology can support 3840x2160@30fps processing and only needs about 133.8K gate count, which can save 53% of gate count when compared with previous work.
Analysis of Color Space and Similarity Measure Impact on Stereo Block Matching
(2008)
Chang, Nelson Yen-Chung
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Tseng, Yu-Cheng
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of color space and similarity measure on complexity, speed, and performance of stereo matching is especially important to applications adopting stereo vision. This work analyzed the complexity of several most commonly considered color space and similarity measure. In addition, the execution speed and performance of color space and similarity measure combination arc also compared on the same basis. The comparison result suggests that the Y-only rank provides the best combination under speed and performance trade-off.
Data and Hardware Efficient Design for Convolutional Neural Network
(2018-05-01)
Lin, Yue-Jin
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Hardware design of deep convolutional neural networks (CNNs) faces challenges of high computational complexity and data bandwidth as well as huge divergence in different CNN network layers, in which the throughput of the convolutional layer would be bounded by available hardware resource, and throughput of the fully connected layer would he hounded by available data bandwidth. Thus, a highly flexible and efficient design is desired to meet these needs. This paper presents an end-to-end CNN accelerator that maximizes hardware utilization with run-time configurations of different kernel sizes. It also minimizes data bandwidth with the output first strategy to improve the data reuse of the convolutional layers by up to 300x ti 600x compared with the non-reused case. The whole CNN implementation of the target network is generated optimally for both hardware and data efficiency under design resource constraints, which can be run-time reconfigured by the layer optimized parameters to achieve real-time and end-to-end CNN acceleration. An implementation example for AlexNet consumes a 1.783 M gate count for 216 MACs and a 142.64 kh internal buffer with TSMC 40 nm process, and achieves 99.7 and 61.6 f/s under 454 MHz clock frequency for the convolutional layers and the whole AlexNet, respectively.
Fast Rate Distortion Optimization Design for HEVC Intra Coding
(2015)
Chang, Jia-Hao
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Various coding structures and modes in the latest High Efficiency Video Coding (HEVC) standard result in significant computation of rate distortion optimization to decide the best one. To fit the real time demand, this paper proposes a hardware-friendly Rate-Distortion Estimation algorithm and its hardware design. For bit rate estimation, we propose a linear model based on the histogram of quantized coefficients instead of serial arithmetic coding computation in the reference software for speedup. For the distortion estimation, we use the transform domain instead of spatial domain estimation to save inverse transform computation. The simulation results shows 3.49% BD-rate increase on average compared to reference software. The hardware implementation with TSMC 90nm CMOS costs 50K logic gates which can support the processing with 16 pixels per cycle at 270MHz operation frequency.
Fast Zero Block Detection and Early CU Termination for HEVC Video Coding
(2013)
Chiang, Pai-Tse
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Chang, Tian Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposed a fast zero block detection for various transform size from 32x32 to 4x4 in the new generation of the High Efficiency Video Coding (HEVC) standard. The derivation is based on sum-of-absolute-difference (SAD) value available in the inter prediction computation. The proposed method achieves detection accuracy to 90% in average, and saves transform unit computation by 44% (QP at 22) and 65% (QP at 32) with negligible coding performance loss, when compared with that of HM4.0rc1. Additionally, this pre-skip detection could further help decide the CU inter mode efficiently with about 50% time saving.
Low Complexity Real Time BCI for Stroke Rehabilitation
(2015)
Chou, Tsung-Pen
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Wang, Wan-Ru
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Stroke rehabilitation with EEG-based brain computer interface enables interaction within injury neurons and restoration of original functions in motor area of brain. However, many approaches usually require high complexity for reliable detection and result in achieving real time computation difficultly. This study proposes a real time low complexity BCI interface for stroke rehabilitation, which is based on Filter-Bank Common Spatial Pattern (FBCSP) method. For reducing complexity purpose, EEG channels (electrodes) are reduced from 19 channels to 4 channels which are Fz, C3, Cz, and C4. Furthermore, the filter bank is reduced from five bands to three bands which are 4-7Hz, 8-12Hz, and 13-30Hz. We also develop a real time scheme by using one-second timing window for EEG analysis and adaptive algorithm to fit time-varying EEG. This approach not only reduces 87% computational complexity but also shows over 80% accuracy for offline analysis and 68% accuracy for online implementation within one-second response time.
Optimal data mapping for motion compensation in H.264 video decoding
(2007)
Yu, Guo-Shiuan
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Long initial access cycles of SDRAM are the major performance burden of motion compensation in a video decoder. To minimize its effect while improve overall available memory bandwidth, this paper presents an optimal data mapping scheme for motion compensation in H.264 video coding. This scheme allocates the video data into suitable address and bank according to the access characteristics of SDRAM access and address transition in motion compensation. The resulted allocation can reduce the required bandwidth of motion compensation by 36% when compared to the previous design for 525SD video sequences.
Run Time Adaptive Network Slimming for Mobile Environments
(2019-01-01)
Chiu, Hong Ming
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Lin, Kuan-Chih
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Modern convolutional neural network (CNN) models offer significant performance improvement over previous methods, but suffer from high computational complexity and are not able to adapt to different run-time needs. To solve above problem, this paper proposes an inference-stage pruning method that offers multiple operation points in a single model, which can provide computational power-accuracy modulation during run time. This method can perform on shallow CNN models as well as very deep networks such as Resnet101. Experimental results show that up to 50% savings in the FLOP are available by trading away less than 10% of the top-1 accuracy.