A Reconfigurable Inverse Transform Architecture Design for HEVC Decoder

Abstract

In this paper, we present a reconfigurable hardware design which can support the inverse transform size from 4x4 to 32x32 in HEVC (High Efficiency Video Coding). We explore the coefficient properties of various inverse transforms such that a base inverse transform unit can be reconfigured or refined to generate other size of inverse transform. The implementation in 90nm technology can support 3840x2160@30fps processing and only needs about 133.8K gate count, which can save 53% of gate count when compared with previous work.