Browsing by Author "Chang, Ting-Chang"

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A characteristic improved technique and analysis with plasma treatment to the electrode on oxide-based resistive random access memory
(2020-03-15)
Lin, Chih-Yang
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Chang, Ting-Chang
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Pan, Chih-Hung
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Chen, Min-Chen
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Xu, You-Lin
A technique was proposed to concentrate the distribution of set voltages. After a plasma treatment, the stability of the high-resistive state (HRS) increased, and the distribution of set voltages was more concentrated at 0.8 V, with a sufficient HRS/LRS resistive ratio (similar to 100x). In addition, the surface of the TiN electrode became rougher, causing oxygen to enter the TiN electrode and form a TiON layer, which acts as an oxygen reservoir. The reservoir is confirmed and the conduction model is supported by both electrical and material analyses. We propose that the observed improvement is due to the difference in the TiN electrode surface. (C) 2019 Published by Elsevier B.V.
A Dual-Gate InGaZnO4-Based Thin-Film Transistor for High-Sensitivity UV Detection
(2019-08-01)
Chen, Po-Hsun
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Tsao, Yu-Ching
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Chien, Yu-Chieh
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Chiang, Hsiao-Cheng
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Chen, Hua-Mao
UV-sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product commercialization is determining the optimal materials that allow for integration of excellent UV-sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV-light-sensing properties of an amorphous InGaZnO4 (IGZO) thin-film transistor with a dual-gate structure and relatively small device size (width/length = 50 mu m/10 mu m) that achieves high sensitivity through a threshold-voltage-(V-th)-adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 10(6). Furthermore, the UV sensitivity of the dual-gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual-gate a-IGZO transistor to be used for high-performance UV sensing while being effectively integrated in display applications.
A fabrication of germanium nanocrystal embedded in silicon-oxygen-nitride layer
(2006)
Tu, Chun-Hao
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Chang, Ting-Chang
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Liu, Po-Tsun
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Liu, Hsin-Chou
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Weng, Chi-Feng
The formation of germanium nanocrystals embedded in silicon-oxygen-nitride (SiON) layer acting as distributed charge storage elements is proposed in this work. A large memory window is observed due to the isolated Ge nanocrystals in the SiON gate stack layer. The Ge nanocrystals were nucleated after the high-temperature oxidation of SiGeN layer. The nonvolatile memory device with the Ge nanocrystals embedded in SiON stack layer exhibits 4 V threshold voltage shift under 7 V write operation. Also, the sequent high-temperature oxidation of the SiGeN layer acting as the blocking oxide is proposed to enhance the performance of nonvolatile memory devices. (c) 2006 The Electrochemical Society.
A low-temperature method for improving the performance of sputter-deposited ZnO thin-film transistors with supercritical fluid
(2009-04-20)
Chen, Min-Chen
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Chang, Ting-Chang
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Huang, Sheng-Yao
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Chang, Kuan-Chang
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Li, Hung-Wei
A low-temperature method, supercritical CO(2) (SCCO(2)) fluid technology, is employed to improve the device properties of ZnO TFT at 150 degrees C. In this work, the undoped ZnO films were deposited by sputter at room temperature and treated by SCCO(2) fluid which is mixed with 5 ml pure H(2)O. After SCCO(2) treatment, the on/off current ratios and threshold voltage of the device were improved significantly. From x-ray photoelectron spectroscopy analyses, the enhancements were attributed to the stronger Zn-O bonds, the hydrogen-related donors, and the reduction in dangling bonds at the grain boundary by OH passivation.
A Method to Determine the Located Region of Lateral Trap Position by Analysis of Three-Level Random Telegraph Signals in n-MOSFETs
(2015-01-01)
Chen, Ching-En
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Chang, Ting-Chang
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You, Bo
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Tsai, Jyun-Yu
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Lo, Wen-Hung
This paper introduces a method to determine the located region of trap position by the analysis of three-level random telegraph signal (RTS) in partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect-transistors. For the cases of two traps, the average time at the 2nd level ((12)) is composed of average emission time of one trap and average capture time of the other. Comparison and analysis of (tau(2)) curves varying with gate voltage in RTS measurements with and without interchanged source/drain can clarify the located regions of the two traps. Moreover, the simplified equations are also considered and used to confirm the trap positions. (C) 2015 The Electrochemical Society. All rights reserved.
A new pixel circuit compensating for brightness variation in lagre size and high resolution AMOLED displays
(2007-12-01)
Lu, Hau-Yan
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Chang, Ting-Chang
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Tai, Ya-Hsing
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Liu, Po-Tsun
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Chi, Sien
A new pixel design and driving method for active-matrix organic light-emitting diode (AMOLED) display using low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) is proposed. The new circuit consists, of five TFTs and one capacitor to eliminate the variation in the threshold voltage of the TFTs, and the drop in the supply voltage in it single frame operation. The proposed pixel circuit has been verified to realize uniform output current by the simulation work using HSPICE software. The simulated error rate of the output current is also discussed in this paper. The novel pixel design has great potential for use in large size and high resolution AMOLED displays.
A novel a-Si TFT pixel circuit with high immunity to the degradation of the TFTs and OLEDs used in AMOLED displays
(2007)
Lu, Hau-Yan
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Liu, Po-Tsun
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Hu, Chin-Wei
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Chang, Ting-Chang
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Chi, Sien
A simple pixel circuit employing a-Si TFT for AMOLED is proposed. The proposed one can eliminate both the threshold voltage shift of the driving TFT and the OLED. The simulation results indicate that the proposed circuit significantly improves the non-uniformity of output current by the new compensation operation.
A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
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Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
A novel self-aligned etch-stopper structure with lower photo leakage for AMLCD and sensor applications
(2006-12-01)
Liang, Chung-Yu
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Gan, Feng-Yuan
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Liu, Po-Tsun
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Yeh, F. S.
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Chen, Stephen Hsin-Li
In this letter, the authors introduce a novel self-aligned etch-stopper sidewall-contact hydrogenated amorphous silicon (a-Si: H) thin-film transistor (ESSC-TFT), which reduces the photo leakage current by more than one order of magnitude and increases the ON-OFF ratio to seven orders of magnitude under back light illumination. Such a TFT will enable high-resolution and high-brightness liquid-crystal displays (LCDs) for next-generation TV, monitor, notebook, and mobile-phone applications. This ESSC-TFT design reduces the volume of a-Si film in which the active region can totally be shielded by the gate metal resulting in the prevention from direct back light illumination. With the sidewall contact, the hole current is reduced due to the smaller contact area between drain/source and a-Si layer. As well as the source, drain parasitic intrinsic resistance of a-Si can be also lessened by the ESSC-TFT structure. Although the defects between etched a-Si and n(+) a-Si film may degrade the ON current, the ESSC-TFT still exhibits higher ON-OFF ratio and lower leakage than the one in traditional etch-stopper (ES)-TFT structure. The ESSC-TFT structure can be used not only for TFT-LCD application but also for the applications that demand high ON-OFF ratio and low-leakage device, such as X-ray image sensor.
A Novel Structural Design Serving as a Stress Relief Layer for Flexible LTPS TFTs
(2019-01-01)
Wang, Yu-Xuan
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Chang, Ting-Chang
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Huang, Shin-Ping
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Tai, Mao-Chou
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Zheng, Yu-Zhe
In this work a novel device structure aiming to suppress the degradations under bending in flexible devices is demonstrated, named as a wing-shape TFT. Investigations of the electrical characteristics and reliabilities are supported by simulations, theoretical calculations, and structural discussions. First, through both electrical and mechanical stress simulation, the regions of degradation are confirmed to occur at the corner of the gate insulator. After long term mechanical stress, behaviors including an abnormal hump, serious threshold voltage (Vth) shifts, on-current increase, and off-current decrease are observed. By extending the active layer, also serving as a stress relief layer, removes the degradation regions away from the main channel. Therefore, the reliability of the devices is dramatically improved. The geometries of the wings in wing-shape TFTs are also in consideration. From results, with different wing lengths, a similar improvement of the reliability is shown, but the on current is enhanced when the wing length is extended. These phenomena are realized as a result of the difference in the effective width. The proposed wing-shape LTPS TFT has its potential and benefits for future flexible displays.
A Novel Structure to Reduce Degradation Under Mechanical Bending in Foldable Low Temperature Polysilicon TFTs Fabricated on Polyimide
(2020-05-01)
Wang, Yu-Xuan
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Chang, Ting-Chang
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Huang, Shin-Ping
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Tai, Mao-Chou
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Zheng, Yu-Zhe
In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (I-ON) increase, and an off-current (I-OFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings.
A novel threshold voltage compensation pixel circuit with high immunity to the supply voltage drop for AMOLED displays
(2006)
Lu, Hau-Yan
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Liu, Po-Tsun
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Chang, Ting-Chang
;
Chi, Sien
;
光電工程學系
A new pixel circuit employing LTPS TFT for AMOLED is proposed. The proposed one can eliminate both the threshold voltage variation of the driving TFT and the supply voltage drop. The simulation results indicate that the proposed circuit significantly improves the non-uniformity of output current by the new compensation operation.
A study of resistive switching effects on a thin FeO(x) transition layer produced at the oxide/iron interface of TiN/SiO(2)/Fe-contented electrode structures
(2010-02-01)
Feng, Li-Wei
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Chang, Chun-Yen
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Chang, Yao-Feng
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Chen, Wei-Ren
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Wang, Shin-Yuan
Large (>10(2)) and stable resistance switching characteristics were demonstrated in TiN/SiO(2)/Fe structure due to the presence of a thin FeO(x) transition layer at the SiO(2)/Fe interface, produced spontaneously during the plasma-enhanced tetraethyl orthosilicate oxide deposition process. Addition of Pt into Fe electrode, i.e., a TiN/SiO(2)/Fe(0.73)Pt(0.27) structure, was observed to improve the data dispersion of switching parameters, associating with the decrease in Fe content inside the FeO(x) layer. Additionally, current-voltage fitting data shows that current transport mechanism is governed by Ohm's law in low voltage region and Pool-Frenkel behavior in high voltage region, consisting with FeO(x) phase transition characteristics.
A study of resistive switching effects on a thin FeOx transition layer produced at the oxide/iron interface of TiN/SiO2/Fe-contented electrode structures
(2010-02-01)
Feng, Li-Wei
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Chang, Chun-Yen
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Chang, Yao-Feng
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Chen, Wei-Ren
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Wang, Shin-Yuan
Large (>10(2)) and stable resistance switching characteristics were demonstrated in TiN/SiO2/Fe structure due to the presence of a thin FeOx transition layer at the SiO2/Fe interface, produced spontaneously during the plasma-enhanced tetraethyl orthosilicate oxide deposition process. Addition of Pt into Fe electrode, i.e., a TiN/SiO2/Fe0.73Pt0.27 structure, was observed to improve the data dispersion of switching parameters, associating with the decrease in Fe content inside the FeOx layer. Additionally, current-voltage fitting data shows that current transport mechanism is governed by Ohm's law in low voltage region and Pool-Frenkel behavior in high voltage region, consisting with FeOx phase transition characteristics.
A Universal Model for Interface-type Threshold Switching Phenomena by Comprehensive Study of Vanadium Oxide-Based Selector
(2017-01-01)
Lin, Chih-Yang
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Chen, Ying-Chen
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Gu, Meiqi
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Pan, Chih-Hung
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Jin, Fu-Yuan
For the first time, a comprehensive study of Vanadium oxide-based selector characteristics with a universal model observed by thermal and electrical induced threshold switching (TS) phenomena at interface is presented in this work. The model can explain that the resistance evolution by thermal temperature in TS behaviors, as well as the resistance gradually increases with cycling ("seasoning effect"). Compatible current density (10(7)similar to 10(9) A/cm(2)) and selectivity (similar to 100) with physical understanding of evolution in energy barrier and MIT metallic state modulation are studied. The results show a promising design guideline for future storage-class memory (SCM) applications.
Abnormal C-V Hump Effect Induced by Hot Carriers in Gate Length-Dependent p-Type LTPS TFTs
(2019-11-01)
Huang, Shin-Ping
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Chen, Po-Hsun
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Tsao, Yu-Ching
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Chen, Hong-Chih
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Zheng, Yu-Zhe
We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) enhancement is due to the reduction of effective length, and the OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage ( ${V}_{\text {th}}$ ) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down.
Abnormal Dual Channel Formation Induced by Hydrogen Diffusion From SiNx Interlayer Dielectric in Top Gate a-InGaZnO Transistors
(2017-03-01)
Chen, Guan-Fu
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chen, Hong-Chih
This letter investigates effects of different channel dimensions in top-gate a-InGaZnO4 thin-film transistors with SiNx interlayer dielectric. In narrow channel devices, hydrogen atoms in the SiNx layer diffuse into the entire active layer, inducing a single channel. However, in wider channel devices, the diffusion distance for hydrogen atoms is insufficient to affect the whole channel, instead inducing a double channel. In addition, under hot carrier stress, narrow and wide channels exhibit different degradation behaviors, with simulations showing a strong electrical field at IGZO near the drain terminal of the main channel, which is unaffected by hydrogen.
Abnormal High Resistive State Current Mechanism Transformation in Ti/HfO2/TiN Resistive Random Access Memory
(2020-02-01)
Zhou, Kuan-Ju
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Chang, Ting-Chang
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Lin, Chih-Yang
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Chen, Chun-Kuei
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Tseng, Yi-Ting
In this letter, the electrical characteristics of Ti/HfO2/TiN resistive random access memory (RRAM) were thoroughly investigated. An abnormal current degradation was seen in the DC sweeping cycle. Both the on-state and off-state current clearly exhibited degradation with time. Next, current fitting analysis was used to investigate the carrier transport mechanisms. The results indicate that the on-state carrier transport mechanism changed from space-charge-limited current into hopping conduction after cycle sweeping. However, the off-state current changes from Schottky thermal emission to hopping conduction. Based on comparisons of different Schottky distances and Schottky barriers, physical models were proposed to explain the abnormal current degradation behavior. Finally, COMSOL electric field simulations were used to show the electric field distribution around the conducting filament (CF), and the conducting model was subsequently verified.
Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors
(2017-01-09)
Tsao, Yu-Ching
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chiang, Hsiao-Cheng
This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software. Published by AIP Publishing.
Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors
(2020-09-30)
Tu, Hong-Yi
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Chang, Ting-Chang
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Tsao, Yu-Ching
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Tai, Mao-Chou
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Tsai, Yu-Lin
Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.