Browsing by Author "Chao, Mango C. -T."

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A hybrid scheme for compacting test responses with unknown values
(2007)
Chao, Mango C. -T.
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Cheng, Kwang-Ting
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Wang, Seongmoon
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Chakradhar, Srimat T.
;
Ei, Wen-Long V.
This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature Registers (MISR). The proposed scheme guarantees no coverage loss for the modeled faults. The proposed hybrid scheme can also be tuned to observe any user-specified percentage of responses for controlling the coverage loss for un-modeled faults. The experimental results demonstrate that, in comparison with a space compactor or an unknown-blocking MISR alone, the hybrid compaction scheme achieves a lower coverage loss without demanding more test-data volume. In addition, we propose a quantitative approach to estimate the required percentage of observable responses for the proposed scheme, directly based on a test-quality metric of un-modeled faults.
A novel array-based test methodology for local process variation monitoring
(2009)
Luo, Tseng-Chin
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Chao, Mango C. -T.
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Wu, Michael S. -Y.
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Li, Kuo-Tsai
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Hsia, Chin C.
As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for IC manufacturing. To monitor local process variation, a large number of DUTs (device-under-test) in close proximity must be measured. In this paper, we presents a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by utilizing the proposed hardware IR compensation and voltage bias elevation. Furthermore, the DUT layout need not be modified for the proposed test structure so that the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.
A Novel Array-Based Test Methodology for Local Process Variation Monitoring
(2011-05-01)
Luo, Tseng-Chin
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Chao, Mango C. -T.
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Wu, Michael Shien-Yang
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Li, Kuo-Tsai
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Hsia, Chin C.
As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.
A Novel Design Flow for Dummy Fill Using Boolean Mask Operations
(2012-08-01)
Luo, Tseng-Chin
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Chao, Mango C. -T.
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Fisher, Philip A.
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Kuo, Chun-Ren
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電子工程學系及電子研究所
Dummy fill has been demonstrated to be an effective technique to reduce process variation and improve manufacturability for advanced integrated circuit (IC) designs. However, the computation load, often several days for a realistic IC design, is a significant portion of the cycle time for delivering first silicon on new or modified designs. In this paper, we propose a novel design flow and dummy-fill algorithm based on Boolean operations, which greatly improves computational efficiency and pattern density uniformity, and enables dummy generation to be combined with the mask-preparation Boolean operations performed by the mask-fabrication facility. Mask data preparation can be performed in parallel with dummy generation and post-dummy simulation checks at the design house, resulting in improved first-silicon cycle time. Experimental results demonstrate these benefits in the context of an advanced foundry process technology.
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
(2009)
Chin, Ching-Yu
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Tsou, Yao-Te
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Chang, Chi-Min
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Chao, Mango C. -T.
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電子工程學系及電子研究所
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package testing instead of in its wafer testing, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
(2011-12-01)
Chao, Mango C. -T.
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Chin, Ching-Yu
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Tsou, Yao-Te
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Chang, Chi-Min
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電子工程學系及電子研究所
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package test instead of in its wafer test, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
Alternate Hammering Test for Application-Specific DRAMs and an Industrial Case Study
(2012)
Huang, Rei-Fu
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Yang, Hao-Yu
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Chao, Mango C. -T.
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Lin, Shih-Chin
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電子工程學系及電子研究所
This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.
An Efficient Hamiltonian-Cycle Power-Switch Routing for MTCMOS Designs
(2012)
Wang, Yi-Ming
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Chen, Shi-Hao
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Chao, Mango C. -T.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Multi-threshold CMOS (MTCMOS) is currently the most popular methodology in industry for implementing a power gating design, which can effectively reduce the leakage power by turning off inactive circuit domains. However, large peak current may be consumed in a power-gated domain during its sleep-to-active mode transition. As a result, major IC foundries recommend turning on power switches one by one to reduce the peak current during the mode transition, which requires a Hamiltonian-cycle routing to serially connect all the power switches. In this paper, we propose an efficient power-switch routing framework, which can effectively and efficiently find a feasible Hamiltonian-cycle routing among power switches without violating the Manhattan distance constraint between any two power switches while handling the irregular placement of the power switches resulting from the hard macros. The proposed framework is compliant to commercial APR tools and has been used in a major design-service company for taping out complex MTCMOS designs.
Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
(2011)
Chen, Kuo-An
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Chang, Tsung-Wei
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Wu, Meng-Chen
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Chao, Mango C. -T.
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Jou, Jing-Yang
While the technology node continually and aggressively scales, the resolution of FIB techniques does not scale as fast. Thus, the percentage of nets which can be observed or repaired through FIB probing or circuit editing is significantly decreased for advanced process technologies, which limits the candidates that can be physically examined through the FIB techniques during the debugging process. This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals. The layout adjustment is made through pre-defined simple operations subject to the design rules and the timing constraints. Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool. The experimental result based on an 90nm technology has demonstrated that the proposed DFD framework can effectively increase the FIB observable and repairable rates under different parameter settings while the overall area and circuit performance remain the same.
Detecting Stability Faults in Sub-threshold SRAMs
(2011)
Lin, Chen-Wei
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Yang, Hao-Yu
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Huang, Chin-Yuan
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Chen, Hung-Hsin
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Chao, Mango C. -T.
Detecting stability faults has been a crucial task and a hot research topic for the testing of conventional super-threshold 6T SRAM in the past. When lowering the supply voltage of SRAM to the subthreshold region, the impact of stability faults may significantly change, and hence the test methods developed in the past for detecting stability faults may no longer be effective. In this paper, we first categorize the subthreshold-SRAM designs into different types according to their bit-cell structures. Based on each type, we then analyze the difference of its stability faults compared to the conventional super-threshold 6T SRAM, and discuss how the stability-fault test methods should be modified accordingly. A series of experiments are conducted to validate the effectiveness of each stability-fault test method for different types of subthreshold-SRAM designs.
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
(2014-05-01)
Luo, Tseng-Chin
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Chao, Mango C. -T.
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Tseng, Huan-Chi
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Goto, Masaharu
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Fisher, Philip A.
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
(2014-05-01)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Tseng, Huan-Chi
;
Goto, Masaharu
;
Fisher, Philip A.
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
Fault Models and Test Methods for Subthreshold SRAMs
(2013-03-01)
Lin, Chen-Wei
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Chen, Hung-Hsin
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Yang, Hao-Yu
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Huang, Chin-Yuan
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Chao, Mango C. -T.
Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.
Fault Models for Embedded-DRAM Macros
(2009)
Chao, Mango C. -T.
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Yang, Hao-Yu
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Huang, Rei-Fu
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Lin, Shih-Chin
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Chin, Ching-Yu
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.
Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique
(2016)
Chang, Wen-Hsiang
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Chen, Li-De
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Lin, Chien-Hsueh
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Mu, Szu-Pang
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Chao, Mango C. -T.
As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and EM constraints. This paper presents a design flow to generate a PDN that can result in minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.
Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique
(2017-08-01)
Chang, Wen-Hsiang
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Lin, Chien-Hsueh
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Mu, Szu-Pang
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Chen, Li-De
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Tsai, Cheng-Hong
As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electromigration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.
Investigation of Gate Oxide Short in FinFETs and the Test Methods for FinFET SRAMs
(2013)
Lin, Chen-Wei
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Chao, Mango C. -T.
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Hsu, Chih-Chieh
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.
Layout-Based Dual-Cell-Aware Tests
(2019-01-01)
Wu, Tse-Wei
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Lee, Dong-Zhen
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Wu, Kai-Chiang
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Huang, Yu-Hao
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Chen, Ying-Yen
Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.
Mathematical Yield Estimation for Two-Dimensional-Redundancy Memory Arrays
(2010)
Chao, Mango C. -T.
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Chin, Ching-Yu
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Lin, Chen-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an induction-based approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a time-consuming simulation to estimate the expected yield, our yield-estimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.
Methodology of Generating Dual-Cell-Aware Tests
(2017-01-01)
Huang, Yu-Hao
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Lu, Ching-Ho
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Wu, Tse-Wei
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Nien, Yu-Teng
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Chen, Ying-Yen
This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.