Browsing by Author "Chao, Pei-Jung"

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Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits
(2019-05-01)
Li, Yiming
;
Chen, Chieh-Yang
;
Chuang, Min-Hui
;
Chao, Pei-Jung
;
電機工程學系
In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal-oxide-semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device's nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device-circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.
Impact of Geometry Aspect Ratio on 10-nm Gate-All-Around Silicon-Germanium Nanowire Field Effect Transistors
(2014-01-01)
Chao, Pei-Jung
;
Li, Yiming
;
交大名義發表
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分子醫學與生物工程研究所
;
電機資訊學士班
In this paper, we study electrical characteristics of gate-all-around (GAA) silicon-germanium (SiGe) nanowire field effect transistors (NWFETS) with different aspect ratio (AR) of channel. Device characteristics: the subthreshold swing (SS), the drain induced barrier lowering (DIBL), and the I-ON/I-OFF ratio are simulated by using three-dimensional quantum mechanically corrected device simulation. Electrical characteristics of 10-nm-gate GAA Si1-xGex NWFET devices are explored with respect to different thickness of SiGe and Ge\'s mole fraction. It is investigated that an ellipse-shaped channel with a small aspect ratio possesses better DC characteristics, compared with the one which has large AR due to its good gate controllability.
Process Variation Effect, Metal-Gate Work-Function Fluctuation and Random Dopant Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFET Devices
(2015)
Li, Yiming
;
Chang, Han-Tung
;
Lai, Chun-Ning
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Chao, Pei-Jung
;
Chen, Chieh-Yang
In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-kappa/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.
Statistical Device Simulation of Characteristic Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFETs Induced by Various Discrete Random Dopants
(2016)
Sung, Wen-Li
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Chang, Han-Tung
;
Chen, Chieh-Yang
;
Chao, Pei-Jung
;
Li, Yiming
We study the impact of random dopant fluctuation (RDF) on electrical characteristics of 10-nm-gatehigh kappa/metal gate gate-all-around silicon nanowire MOSFET devices. To provide the best accuracy of device simulation, model parameters are validated by using full quantum mechanical simulation and calibrated with experimental results. Physical mechanism of RDs inside channel and penetration from the source/drain extensions into the channel is discussed. Electrical characteristic of the device is estimated with respect to different types of RDF.
Timing and Power Fluctuations on Gate-All-Around Nanowire CMOS Circuit Induced by Various Sources of Random Discrete Dopants
(2017-01-01)
Sung, Wen-Li
;
Chao, Pei-Jung
;
Li, Yiming
;
分子醫學與生物工程研究所
;
電信工程研究所
Random dopant fluctuation (RDF) is one of fluctuation sources in sub-7-nm semiconductor technology node. In this paper, we estimate the timing and power fluctuations on 10-nm-gate gate-all-around (GAA) silicon nanowire (NW) complementary metal-oxide-semiconductor (CMOS) circuit induced by various random discrete dopants (RDDs) from channel (with/without doping), source/drain (S/D) extensions and penetration from S/D extensions. The 3D quantum mechanical transport and non-equilibrium Green's function (NEGF) models were used for the NW CMOS circuit. The experimentally validated device simulation indicates that at a similar threshold voltage, CMOS devices without channel doping possess 49.5% reduction on the normalized fluctuation of the static power consumption due to the reduction of sigma V-th and sigma I-off. The normalized fluctuation of dynamic power is comparable with/without channel doping due to small variation of the gate capacitance. Because of reduction of sigma I-sat, the normalized fluctuation of short-circuit power of CMOS circuit was reduced from 21.7% to 10.2% without channel doping. And, we found that the uctuations of the timing, noise margin (NM) and power consumption of the NW CMOS circuit follow the trend of sigma V-th. From the point of view of N-/P-type NW MOSFETs caused by RDF, this study may show the fluctuation of CMOS circuit performance highly influenced by the key parameters of N-/P-type NW MOSFETs.