Browsing by Author "Chao, Tien-Sheng"

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3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
;
Lu, Yu-Lun
;
Hsueh, Fu-Kuo
;
Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
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Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
A Novel Ion-Bombarded and Plasma-Passivated Charge Storage Layer for SONOS-Type Nonvolatile Memory
(2012-10-01)
Liu, Sheng-Hsien
;
Yang, Wen-Luh
;
Wu, Chi-Chang
;
Chao, Tien-Sheng
;
電子物理學系
A novel technique combination of ion bombardment (IB) and NH3 plasma treatment (PT) has been presented to yield a highly effective charge storage layer for Si/SiO2/Si3N4/SiO2/Si (SONOS)-type nonvolatile memory applications. The IB technique creates additional trap sites within the charge storage layer strikingly to enhance the charge trapping/detrapping efficiency of the storage layer, and the NH3 PT passivates shallow trap sites significantly to improve reliability characteristics. The distribution of trap sites corresponding with various energy levels is clearly described by discharge-based multipulse analysis. As compared with the control sample (without IB and NH3 PT), the ion-bombarded and NH3-plasma-passivatedmemory device has faster program/erase speeds and larger memory window. In addition, the competent reliability properties of the ion-bombarded and NH3-plasma-passivated memory, such as good endurance, long data retention, and acceptable disturbance, were also demonstrated in this letter.
A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
A simple method for sub-100 nm pattern generation with I-line double-patterning technique
(2010-05-01)
Tsai, Tzu-I
;
Lin, Horng-Chih
;
Jian, Min-Feng
;
Huang, Tiao-Yuan
;
Chao, Tien-Sheng
We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal-oxide-semiconductor field-effect transistors. Excellent device characteristics were verified. (C) 2010 Elsevier Ltd. All rights reserved.
Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application
(2014-10-28)
Chin, Fun-Tat
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Lin, Yu-Hsien
;
You, Hsin-Chiang
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Yang, Wen-Luh
;
Lin, Li-Min
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.
Al-SiO2-Y2O3-SiO2-poly-Si Thin-Film Transistor Nonvolatile Memory Incorporating a Y2O3 Charge Trapping Layer
(2013)
Pan, Tung-Ming
;
Yen, Li-Chen
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Mondal, Somnath
;
Lo, Chieh-Ting
;
Chao, Tien-Sheng
In this letter, we investigate the structural properties and electrical characteristics of the Al-SiO2-Y2O3-SiO2-poly-Si (AOYOP) thin-film transistor (TFT) nonvolatile memory device. The composition of Y2O3 charge-trapping layer was analyzed using X-ray photoelectron spectroscopy. The Y2O3 AOYOP TFT memory device exhibited a large memory window of 2.5 V, a long charge retention time of ten years with a minimal charge loss of similar to 15%, and a better endurance performance for P/E cycles up to 10(5). (c) 2013 The Electrochemical Society. All rights reserved.
Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing
(2011-07-01)
Hsueh, Fu-Kuo
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Lee, Yao-Jen
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Lin, Kun-Lin
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Current, Michael I.
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Wu, Ching-Yi
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 x 10(15) ion/cm(2), were annealed by microwave methods at temperatures below 500 degrees.C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross-sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.
Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
(2010-04-01)
Liao, Chia-Chun
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Chiang, Tsung-Yu
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Lin, Min-Chen
;
Chao, Tien-Sheng
;
電子物理學系
In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film.
Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors
(2011-04-01)
Ma, William Cheng-Yu
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Chiang, Tsung-Yu
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Yeh, Chi-Ruei
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Chao, Tien-Sheng
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Lei, Tan-Fu
In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility mu FE, rising from 14.33 to 22.33 cm(2)/V . s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility mu FE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified.
Channel Thickness Effect on High-Frequency Performance of Poly-Si Thin-Film Transistors
(2013-08-01)
Chen, Kun-Ming
;
Tsai, Tzu-I
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Lin, Ting-Yao
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Lin, Horng-Chih
;
Chao, Tien-Sheng
In this letter, we present the high-frequency performances of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a nominal gate length of 0.22 mu m. Owing to the short gate length and adoption of salicide process, cutoff frequency (f (T)) of 17 GHz and maximum oscillation frequency of similar to 21 GHz are obtained. The result suggests that the poly-Si TFT technology is applicable to RF integrated circuits up to 2 GHz. In addition, we also investigate the effects of channel thickness on the high-frequency characteristics of poly-Si TFTs. We find that the variation of f (T) with channel thickness is mainly due to the change in transconductance.
Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface Treatment
(2008-12-01)
Ma, Ming-Wen
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Chiang, Tsung-Yu
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Wu, Woei-Cherng
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Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO(2) gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO(2)/poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO(2) LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO(2) gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel.
Characteristics of In0.7Ga0.3As MOS Capacitors Obtained using Hydrochloric Acid Treatment, Ammonium Sulfide Passivation, Methanol Treatment, and Forming Gas Annealing
(2019-08-14)
Chung, Sheng-Ti
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Huang, Yi-Chin
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Fu, Yen-Chun
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Lee, Yao-Jen
;
Chao, Tien-Sheng
This paper proposes a chemical pre-treatment process to reduce sulfate prior to atomic layer deposition of Al2O3 gate dielectrics on n-doped In0.7Ga0.3As layers to form metal oxide semiconductor capacitors (MOSCAPs). Cleaning with methanol was done after hydrogen chloride etching and ammonium sulfide passivation. X-ray photoelectron spectroscopy performed on the sample with methanol cleaning indicated that its native oxide regrowth was effectively prevented on the sulfur-passivated In0.7Ga0.3As surface under air exposure. By analysis using atomic force microscopy of the sample cleaned using methanol, no further increase of surface roughness was observed after 5 months of air exposure. In addition, a mid-gap interface defect density (D-it) of 1.3 x 10(12) cm(-2) eV(-1) was obtained from this sample. After forming gas annealing (FGA), the D-it was improved significantly, to a value below 10(12) cm(-2) eV(-1). The obtained data indicate that the combination of chemical pre-treatment and FGA is advantageous to passivating the trap states on In0.7Ga0.3As MOSCAPs. (C) 2019 The Electrochemical Society.
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
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Chen, Chih-Yang
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Su, Chun-Jung
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Wu, Woei-Cherng
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Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing
(2020-01-01)
Chung, Sheng-Ti
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing ferroelectric effects. The ferroelectric layers were deposited on JL-FinFETs. The poly-Si junctionless FinFETs (JL-FinFETs) with HfZrO were successfully fabricated and demonstrated. The subthreshold slope (S.S.) of JL-FinFETs with HfZrO was very sensitive to post-metal annealing (PMA) conditions and fin width. With PMA at 700 & x00B0;C, steeper S.S. and I_on& x002F;I_off> 10(7) could be obtained owing to the ferroelectric effect. JL-FinFETs with PMA at 700 & x00B0;C possessed lower I_off and offered the promise of higher integration flexibility for Si CMOS compatible process for future applications. Besides, the JL-FinFETs with forming gas annealing (FGA) had a small hysteresis and achieved the improved S.S.
Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratio
(2007-05-01)
Kuo, Po-Yi
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Chao, Tien-Sheng
;
Hsieh, Pei-Shan
;
Lei, Tan-Fu
;
電子物理學系
In this paper, we have successfully developed and fabricated self-aligned Si/Ge T-gate poly-Si thin-film transistors (Si/Ge T-gate TFTs) with a thick gate oxide at the gate edges near the source and drain for the first time. The Si/Ge T-gate was formed by selective wet etching of Ge gate layer. The thick gate oxide layer at the gate edges and passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, lightly doped drain, spacer, or subgate bias. The Si/Ge T-gate TFTs not only,reduce the OFF-state leakage current but also maintain a high ON-state current. Experimental results show that the Si/Ge T-gate TFTs have low OFF-state leakage currents, improved ON/OFF current ratio, and more saturated output characteristics compared with conventional TFTs.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering
(2011-04-01)
Lu, Tsung-Yi
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Chang, Tien-Shun
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Huang, Shih-An
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Chao, Tien-Sheng
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電子物理學系
To extend a carrier mobility improvement by strain engineering in high-density and small-gate-space complementary metal-oxide-semiconductor (CMOS) circuits, we have proposed a new stress memorization technique (SMT) that uses a strain proximity free technique (SPFT) to demonstrate the mobility improvement through multiple strain-gate engineering. The electron mobility of n-channel metal-oxide-semiconductor (MOS) field-effect transistors with the SPFT exhibits a 14% increase over counterpart techniques. Compared with the conventional SMT, the SPFT avoids the limitation of the stressor volume for the performance improvement in high-density CMOS circuits. We also found that the preamorphous layer (PAL) gate structure in combination with the SPFT can improve the mobility further to 31% greater than standard devices. Moreover, an additional 30% mobility enhancement can be achieved by using a dynamic threshold-voltage MOS and combining the PAL gate structure with the SPFT, respectively. The gate-oxide reliability and the channel-hot-carrier reliability are also analyzed. Our results show a mobility improvement by the SPFT, a slightly increased gate leakage current, and degraded channel-hot-carrier reliability.
Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal
(2014)
Wu, Chien-Ting
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Lee, Yao-Jen
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Hsueh, Fu-Kuo
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Sung, Po-Jung
;
Cho, Ta-Chun
A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.