Browsing by Author "Chen, Chao-Jui"

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Ir Nanocrystals on Asymmetric Si(3)N(4)/SiO(2) Tunneling Layer with Large Memory Window for Nonvolatile Memory Application
(2011-04-01)
Wang, Terry Tai-Jui
;
Chen, Chao-Jui
;
Teng, I-Ju
;
Hsieh, Ing-Jar
;
Kuo, Cheng-Tzu
The capacitance-voltage measurements and microstructures of Iridium-nanocrystals embedded in two main stack devices of "Al/SiO(2)/Ir-NCs/SiO(2)/Si-Sub/Al" and "Al/SiO(2)/Ir-NCs/Si(3)N(4)/SiO(2)/SiSub/Al" have been compared for the application of nonvolatile memory. It has been demonstrated that the device performance of Si(3)N(4)/SiO(2) tunneling bi-layer (former stack) is much better than the single SiO(2) tunneling layer in terms of program/erase (P/E) efficiency and memory window size (up to 12.6 V at +/-10 V sweeping voltages), though 5% degrade in data retentions. Furthermore, endurances of two devices can stand 10(4) cycles without failure under P/E stressing condition of +/-9 V, 100 ms.
Ir Nanocrystals on Asymmetric Si3N4/SiO2 Tunneling Layer with Large Memory Window for Nonvolatile Memory Application
(2011-04-01)
Wang, Terry Tai-Jui
;
Chen, Chao-Jui
;
Teng, I-Ju
;
Hsieh, Ing-Jar
;
Kuo, Cheng-Tzu
The capacitance-voltage measurements and microstructures of Iridium-nanocrystals embedded in two main stack devices of "Al/SiO2/Ir-NCs/SiO2/Si-Sub/Al" and "Al/SiO2/Ir-NCs/Si3N4/SiO2/SiSub/Al" have been compared for the application of nonvolatile memory. It has been demonstrated that the device performance of Si3N4/SiO2 tunneling bi-layer (former stack) is much better than the single SiO2 tunneling layer in terms of program/erase (P/E) efficiency and memory window size (up to 12.6 V at +/-10 V sweeping voltages), though 5% degrade in data retentions. Furthermore, endurances of two devices can stand 10(4) cycles without failure under P/E stressing condition of +/-9 V, 100 ms.