Ir Nanocrystals on Asymmetric Si(3)N(4)/SiO(2) Tunneling Layer with Large Memory Window for Nonvolatile Memory Application

Abstract

The capacitance-voltage measurements and microstructures of Iridium-nanocrystals embedded in two main stack devices of "Al/SiO(2)/Ir-NCs/SiO(2)/Si-Sub/Al" and "Al/SiO(2)/Ir-NCs/Si(3)N(4)/SiO(2)/SiSub/Al" have been compared for the application of nonvolatile memory. It has been demonstrated that the device performance of Si(3)N(4)/SiO(2) tunneling bi-layer (former stack) is much better than the single SiO(2) tunneling layer in terms of program/erase (P/E) efficiency and memory window size (up to 12.6 V at +/-10 V sweeping voltages), though 5% degrade in data retentions. Furthermore, endurances of two devices can stand 10(4) cycles without failure under P/E stressing condition of +/-9 V, 100 ms.