Browsing by Author "Chen, Chi-Lin"

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800V Ultra-High-Voltage Start-up Mechanism for Pre-regulator in Power Factor Correction (PFC) Controller
(2011)
Chen, Chi-Lin
;
Tsai, Jen-Chieh
;
Chen, Yi-Ting
;
Ni, Chia-Lung
;
Chen, Chun-Yen
The on-chip 800V ultra-high-voltage (UHV) start-up mechanism was introduced in this paper. Using the UHV start-up mechanism can minimize the current leakage at the AC input and remove the need of external start-up resistor and capacitor. As a result, the standby current can be decreased to improve the efficiency of AC-DC systems. Furthermore, the zero current detection (ZCD) circuit was used here to ensure the work of the pre-regulator. An inductance coil will detect the primary inductance current and reflect the voltage, which is detected by ZCD circuit to provide the energy to the pre-regulator. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Certainly, high efficiency of 95% can be ensured at the output power of 50W.
A Charge-Reservoir with Buck-Store and Boost-Restore (BSBR) Technique for High Efficient Conversion and Low Cost Solution of RGB LED Display Panels
(2009)
Hsieh, Chun-Yu
;
Yang, Chih-Yu
;
Huang, Ming-Hsin
;
Li, Don-Hwan
;
Chen, Chi-Lin
A boost converter with buck-store and boost-restore (BSBR) technique fabricated by 0.25 mu m CMOS BCD process can provide different supply voltages to drive series RGB LEDs in sequence for reducing the power consumption on the constant current generator. The proposed technique not only stores and restores extra charge during the transient time of the reference tracking response to improve the efficiency but also enhances the reference tracking response to greatly reduce load transition time. Experimental results show that the period of reference-tracking response can be improved. When the load current is 100mA, the periods of reference down-tracking and up-tracking are smaller than lops and 20 mu s, respectively. Furthermore, this technique also can provide a regulated voltage to drive the sub-block implemented in the LCD system. The maximum efficiency of charge recycling is up to 94% and the maximum efficiency of this boost converter is 92.5%. Experimental results demonstrate fast and efficient reference tracking performance is achieved by the proposed BSBR technique.
Adaptive Window Control (AWC) Technique for Hysteresis DC-DC Buck Converters With Improved Light and Heavy Load Performance
(2009-05-01)
Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Chen, Ke-Horng
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a new adaptive window control (AWC) technique to adjust the hysteresis window to reduce the output ripple at heavy loads and keep the switching frequency higher than the acoustic frequency at light loads. Therefore, the driving capability and the power conversion efficiency of the hysteresis converter are improved at heavy loads. Besides, a new class AB current sensing circuit is also proposed to provide fast and accurate current sensing signal for achieving fast hysteresis window adjustment. Experimental results show that the proposed AWC technique not only reduces the output ripple smaller than 12 mV when load current is 800 mA to improve the power conversion efficiency but also keeps the switching frequency higher than acoustic frequency at light loads to avoid undesired noise.
Current Feedback Compensation (CFC) Technique for Adaptively Adjusting the Phase Margin in Capacitor-Free LDO Regulators
(2008-01-01)
Yang, Huan-Chien
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Huang, Han-Hsiang
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Chen, Chi-Lin
;
Huang, Ming-Hsin
;
Chen, Ke-Homg
Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 mu A without sacrificing bandwidth at tight load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique [6]. The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mu m 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to 50 mu A and transient response time with adaptively phase margin control is smaller than 1 mu s.
Current Feedback Compensation (CFC) Technique for Adaptively Adjusting the Phase Margin in Capacitor-Free LDO Regulators
(2008-01-01)
Yang, Huan-Chien
;
Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Huang, Ming-Hsin
;
Chen, Ke-Homg
Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 mu A without sacrificing bandwidth at tight load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique [6]. The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mu m 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to 50 mu A and transient response time with adaptively phase margin control is smaller than 1 mu s.
Fast Mode-Switching Technique in Hrbrid-Mode Operation
(2008)
Chen, Chi-Lin
;
Hsieh, Wei-Lun
;
Huang, Han-Hsiang
;
Chen, Ke-Horng
;
電控工程研究所
A fast mode-switching technique between pulse width modulation (PWM) and pulse frequency modulation (PFM) modes Is proposed to keep high efficiency over wide load range. Load dependent zero-current detector (ZCD) can effectively speed up the transition from PWM to PFM mode. Especially, the overshoot voltage can be minimized by using the reversed current provided by the ZCD circuit. Furthermore, the undershoot voltage of the transition from PFM to PWM mode can be reduced because the recovery time can be reduced by restoring the output voltage of the error amplifier. Thus, the efficiency of current mode DC-DC buck converter is higher than 88% at light loads and the recovery time is smaller than 35 mu s when load current changes from 500mA to 10mA suddenly.
High-Efficiency Slope Compensator (HSC) with Input-Independent Load Condition Identification in Current Mode DC/DC Buck Converters
(2009)
Lai, Wei-Jen
;
Chen, Chi-Lin
;
Hsieh, Yu-Chiao
;
Chen, Ke-Horng
;
電控工程研究所
A high-efficiency slope compensator (HSC) is presented to achieve power reduction in current-mode control and provide input-independent load condition identification for mode switch in hybrid PWM/PFM system. That is, according to load condition, an adaptive mode transition can be decided by the HSC circuit and not varied by the variation of input voltage. Therefore, for a hybrid PWM/PFM system, the power conversion efficiency can be kept high over a wide load range. Besides; the pulse-ramp slope compensation technique prevents the current-mode DC-DC converter from having the sub-harmonic oscillation problem and reduces power dissipation of the slope compensator. Simulation results show that the mode transition is accurately decided at the optimum point without being affected by the variation of input voltage. The power conversion efficiency is improved about 5% in PWM/PFM transition region.
Modified Hysteretic Current Control (MHCC) for Improving Transient Response of Boost Converter
(2011-08-01)
Tsai, Jen-Chieh
;
Chen, Chi-Lin
;
Lee, Yu-Huei
;
Yang, Hong-Yuan
;
Hsu, Ming-Shen
This paper proposes a modulated hysteretic current control (MHCC) technique to improve the transient response of a DC-DC boost converter, which suffers from low bandwidth due to the existence of the right-half-plane (RHP) zero. The MHCC technique can automatically adjust the on-time value to rapidly increase the inductor current, as well as to shorten the transient response time. In addition, based on the characteristic of the RHP zero, the compensation poles and zero are deliberately adjusted to achieve fast transient response in case of load transient condition and adequate phase margin in steady state. Experimental results show the improvement of transient recovery time over 7.2 times in the load transient response compared with the conventional boost converter design when the load current changes from light to heavy or vice versa. The power consumption overhead is merely 1%.
Perturbation On-time (POT) Control and Inhibit Time Control (ITC) in Suppression of THD of Power Factor Correction (PFC) Design
(2011)
Tsai, Jen-Chieh
;
Chen, Chi-Lin
;
Chen, Yi-Ting
;
Ni, Chia-Lung
;
Chen, Chun-Yen
The paper presented the perturbation on-time (POT) control technique to suppress the total harmonic distortion (THD) to improve the performance of the power factor correction (PFC) in the AC-DC converter. Simultaneously, it can improve the efficiency through the proposed inhibit time control (ITC) mechanism at low AC input voltage. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Besides, high efficiency of 95% can be ensured at the output power of 90W.
Perturbation On-Time (POT) Technique in Power Factor Correction (PFC) Controller for Low Total Harmonic Distortion and High Power Factor
(2013-01-01)
Tsai, Jen-Chieh
;
Chen, Chi-Lin
;
Chen, Yi-Ting
;
Ni, Chia-Lung
;
Chen, Chun-Yen
The proposed perturbation on-time technique suppresses total harmonic distortion (THD) and, thus, improves the power factor in the power factor correction (PFC) controller. Besides, the adaptive control of the minimum off time by the proposed inhibit time control can improve efficiency even at low ac input voltage. Therefore, highly integrated PFC converter fabricated in the TSMC 800-V ultrahigh voltage process can achieve low THD of 6%, high PF of 99%, and high efficiency of 95% at the output power of 90 W.
Solid-Duty-Control Technique for Alleviating the Right-Half-Plane Zero Effect in Continuous Conduction Mode Boost Converters
(2012-01-01)
Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Wu, Dian-Rung
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Chen, Ke-Horng
;
電控工程研究所
This paper proposes a solid-duty-control (SDC) technique for application in boost converters to maintain a constant duty value and reduce dip voltage during load transient periods. Fast transient response was also achieved because of the variable transient enhancement controller. The proposed SDC technique can provide a stable and regulated output for edge-lit light-emitting diode backlight systems. This converter was used in a 0.25-mu m CMOS process. Experimental results show that compared with a conventional design without a fast transient technique, the proposed approach yields about 30% and 80% improvement in undershoot voltage and recovery time, respectively, as load current changes from 50 to 250 mA.
Triple Loop Modulation (TLM) for High Reliability and Efficiency in a Power Factor Correction (PFC) System
(2013-07-01)
Tsai, Jen-Chieh
;
Ni, Chia-Lung
;
Chen, Chi-Lin
;
Chen, Yi-Ting
;
Chen, Chun-Yen
The proposed triple loop modulation (TLM) can ensure reliability of the power factor correction (PFC) system due to the improvement of transient response. In conventional design, low bandwidth of less than 20Hz that rejects ac source of 60/120 Hz coupling deteriorates system reliability in case of output load variation. Contrarily, the proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current to shorten transient response time. Besides, in the steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by the TLM. The test circuit fabricated in a VIS 500 V UHV laterally diffused metal-oxide-semiconductor transistor process demonstrates that the highly integrated PFC controller with the proposed TLM has high power factor of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than in conventional PFC design with output load variation from 90 to 20W and vice versa.
Triple Loop Modulation (TLM) for High Reliability and Efficiency in Power Factor Correction (PFC) System
(2012)
Tsai, Jen-Chieh
;
Ni, Chia-Lung
;
Chen, Chun-Yen
;
Chen, Yi-Ting
;
Chen, Chi-Lin
Reliability of the Power Factor Correction (PFC) system was improved by fast transient response using the proposed triple loop modulation (TLM). Low bandwidth of less than 20 Hz that rejects AC source of 60/120 Hz coupling deteriorated system reliability in case of output load variation. The proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current in order to shorten transient response time. In steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. The test circuit fabricated in VIS 500 V UHV LDMOS process demonstrated the performance of the highly-integrated PFC controller with the proposed TLM. Experimental results showed that the PFC system with TLM has high PF of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than conventional PFC design with output load variation from 90W to 45 W and vice versa.
Zero current detection technique for fast transient response in buck DC-DC converters
(2008)
Chen, Chi-Lin
;
Lai, Wei-Jen
;
Liu, Ter-Hsing
;
Chen, Ke-Horng
;
電控工程研究所
A load dependent zero-current detector is proposed in this paper for speeding up the transient response when load current changes from heavy to tight loads. The fast transient control signal determines how long the reversed inductor current according to sudden load variations. At the beginning of load variation from heavy to tight loads, the sensed voltage compared with higher voltage to discharge the overshoot output voltage for achieving fast transient response. Besides, for an adaptive reversed current period, the fast transient mechanism is turned off since the output voltage is rapidly regulated back to the acceptable level. Simulation results demonstrate that the ZCD circuit permits the reverse current flowing back into n-type power MOSFET at the beginning of load variations. The settling time is decreased to about 35 mu s when load current suddenly changes from 500mA to 10 mA.