Browsing by Author "Chen, Chia-Min"

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A Capacitor-Free CMOS Low-Dropout Voltage Regulator
(2009)
Chen, Chia-Min
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Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This paper presents novel frequency compensation techniques for low-dropout (LDO) voltage regulator. An enhanced active feedback frequency compensation is employed to improve its frequency response. This LDO can provide high stability for loading current range up to 100 mA without loading capacitors. Moreover, the total compensation capacitors only require 7 pF for this technique. This allows us to integrate the compensation capacitors within the LDO chip easily. The proposed LDO regulator was designed using TSMC 0.35-mu m CMOS technology. With an active area of 0.14 mm(2), the quiescent current is only 40 mu A. The input voltage is ranged from 1.73 V to 5 V for loading current of 100 mA and the output voltage of 1.5 V. The main advantage of this approach is that the LDO circuit can be stable when we connect external load capacitors with ultra low ESR, or even when we eliminate the load capacitors.
A crystalline low-bandgap polymer comprising dithienosilole and thieno[3,4-c] pyrrole-4,6-dione units for bulk heterojunction solar cells
(2011-06-08)
Yuan, Mao-Chuan
;
Chou, Yi-Jen
;
Chen, Chia-Min
;
Hsu, Chang-Lung
;
Wei, Kung-Hwa
We have used Stille coupling polymerization to synthesize a new low-bandgap conjugated polymer, PDTSTPD, that consists of an electron-rich dithieno[3,2-b:2',3'-d]-silole (DTS) unit and an electron-deficient thieno[3,4-c]pyrrole-4,6-dione (TPD) moiety. The polymer exhibited an excellent thermal stability, crystalline characteristics, a broad spectral absorption, and a deep highest occupied molecular orbital (HOMO) energy level, resulting from combination of the rigid TPD and the coplanar DTS units in the polymer backbone. Moreover, the presence of the silicon atoms along the polymer chain ensured PDTSTPD having strong interchain stacking and good hole mobility. An optimal device incorporating the PDTSTPD:PC(71)BM blend at a weight ratio of 1:1 provided a power conversion efficiency of 3.42%. (c) 2011 Elsevier Ltd. All rights reserved.
A Fourth-Order FeedForward Continuous-Time Delta-Sigma ADC with 3MHz Bandwidth
(2010)
Huang, Sheng-Wen
;
Chen, Zong-Yi
;
Hung, Chung-Chih
;
Chen, Chia-Min
;
電機工程學系
A fourth-order feedforward continuous-time (CT) delta-sigma modulator is presented. The modulator takes an active-RC OpAmp as the first stage because of the high-linearity requirement, and the other three stages are composed by Gm-C integrators. In feedforward topology, a higher out-of-band NTF gain could be taken for better performance. As we know, the most important part in the feedforward CT Delta Sigma modulator is the summation circuit for the feedforward paths. The modulator uses a tuning adder, which we propose, to make sure the modulator can work correctly even under the influence of the process variation on resistors. Finally, the delta-sigma modulator is implemented in standard digital 0.18-mu m CMOS process, which achieves 57.84 dB SNDR over a 3MHz signal bandwidth at an OSR of 16.67. The power consumption of the CT delta-sigma modulator is 11.8 mW from the 1.8-V supply.
A High Efficiency Current-Mode DC-DC Step-Down Converter with Wide Range of Output Current
(2010)
Chen, Chia-Min
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Hsu, Kai-Hsiu
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a high efficiency current-mode DC-DC step-down converter with wide range of output current. The converter adaptively operates as Pulse-Width Modulation (PWM). An on-chip current sensing technique is employed to reduce external components and no extra I/O pins are needed for the current-mode controller. A soft-start operation is designed to eliminate the excess large current during the startup of the regulator. The circuit has been designed with TSMC 2P4M 0.35 mu m CMOS process. The range of the supply voltage is from 2 to 5V, which is suitable for single-cell lithium-ion battery.
A low-glitch binary-weighted DAC with delay compensation scheme
(2014-05-01)
Chou, Fang-Ting
;
Chen, Chia-Min
;
Hung, Chung-Chih
;
資訊工程學系
;
Department of Computer Science
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Omega termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 mu m CMOS technology and dissipates 19 mW from a single 1.8 V power supply.
A low-power CMOS voltage reference circuit based on subthreshold operation
(2007)
Chang, Chia-Wei
;
Lo, Tien-Yu
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Chen, Chia-Min
;
Wu, Kuo-Hsi
;
Hung, Chung-Chih
A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-mu m CMOS process. The voltage reference circuit uses the V-GS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient The reference voltage can be obtained by combining the weighted V-GS difference with weak-inversion V-GS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/degrees C in [-20 degrees C-120 degrees C] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm(2) and dissipates 17.25 mu W at room temperature. By connecting a 0.22 mu F loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 mu V/root Hz and 22.2 mu V/root Hz, respectively.
A nanostructured micellar diblock copolymer layer affects the memory characteristics and packing of pentacene molecules in non-volatile organic field-effect transistor memory devices
(2013)
Chen, Chia-Min
;
Liu, Chih-Ming
;
Tsai, Ming-Chang
;
Chen, Hsiu-Cheng
;
Wei, Kung-Hwa
Organic field-effect transistor (OFET) memory devices incorporating the copolymer polystyrene-block-poly(4-vinylpyridine) (PS56k-b-P4VP(8k)) layer, which features a thickness-dependent micellar nanostructure (P4VP-core, PS-shell), as a charge trapping layer can exhibit tunable memory windows for p-channel applications. For instance, the memory window increased substantially from 7.8 V for the device incorporating a 60 nm thick PS56k-b-P4VP(8k) layer to 21 V for the device incorporating a 27 nm thick layer, an increase of more than 2.5 times. Using simultaneous synchrotron grazing-incidence small-angle X-ray scattering and wide-angle X-ray scattering to probe the nanostructured micellar PS56k-b-P4VP(8k) layer and the pentacene layer positioned directly on the top of the copolymer layers, respectively, we were able to elucidate the structural characteristics of the bilayer and to correlate their effects with the memory performances of devices with similar architectures. For the PS56k-b-P4VP(8k) layers, we found that the inter-micelle distance and their lateral arrangements depended on the layer thickness: the thickness of the PS shells in the lateral direction decreased upon increasing the layer thickness, as did the memory window for the OFET device that incorporated the PS56k-b-P4VP(8k) layers, showing a strong dependence of the threshold voltage shifts (i.e., memory window) on the distance between the micelles. Additionally, for the molecular packing of the pentacene layer positioned on the copolymer layer, we found that the PS56k-b-P4VP(8k) layers affected not only the orientation of the pentacene molecules but also their grain sizes, thereby affecting the hole mobility of the memory devices. These results suggest that tuning the micellar nanostructure of the block copolymer thin film that was used as a trapping layer can be a simple and effective way for optimizing the memory window and affecting the hole mobility of OFET memory devices.
A Novel Glitch Reduction Circuitry for Binary-Weighted DAC
(2014-01-01)
Chou, Fang-Ting
;
Chen, Chia-Min
;
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機資訊學士班
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm(2) core area, and dissipates 19mW from a single 1.8V power supply.
A Thieno[3,4-c]pyrrole-4,6-dione-Based Donor-Acceptor Polymer Exhibiting High Crystallinity for Photovoltaic Applications
(2010-09-14)
Yuan, Mao-Chuan
;
Chiu, Mao-Yuan
;
Liu, Shih-Pin
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Chen, Chia-Min
;
Wei, Kung-Hwa
An Inductor-Coupling Resonated CMOS Low Noise Amplifier for 3.1-10.6GHz Ultra-Wideband System
(2009)
Huang, Zhe-Yang
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Huang, Che-Cheng
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Chen, Chun-Chieh
;
Hung, Chung-Chill
;
Chen, Chia-Min
In this paper, a low power low-noise amplifier (LNA) using inductor-coupling resonated technique is designed for ultra-wideband (UWB) wireless system. The design consists of a wideband input impedance matching network, one stage cascode amplifier with inductor-coupling resonated load, and an output buffer; it was fabricated in TSMC 0.18um standard RF CMOS process. The UWB LNA gives 10.8dB power gain and 9.4GHz 3dB bandwidth (1.2GHz - 10.6GHz) while consuming only 6.2mW through a 1.2V supply, including output buffer. Over the 3.1GHz - 10.6GHz frequency band, a minimum noise figure of 3.9dB and input return loss lower than -5.7dB have been achieved.
Carbazole-Based Conjugated Polymers Incorporating Push/Pull Organic Dyes: Synthesis, Characterization, and Photovoltaic Applications
(2010-11-15)
Hsu, So-Lin
;
Chen, Chia-Min
;
Wei, Kung-Hwa
;
材料科學與工程學系
;
Department of Materials Science and Engineering
We have synthesized and characterized two new carbazole-based conjugated polymers, PCDCN and PCDTA, incorporating two strong light-absorbing organic dyes. These polymers exhibit relatively low band gaps (similar to 1.5 eV) and broad absorption ranges (from 300 to 700 nm). We fabricated polymer solar cells incorporating these polymers as donors and [6,6]-phenyl-C(71)-butyric acid methyl ester (PC(71)BM) as the acceptor. At a blending ratio of 1: 4, we obtained power conversion efficiencies, under simulated AM 1.5 (100 mW/cm(2)) conditions, of 2.31% and 2.47% for the PCDCN- and PCDTA-based devices, respectively. (C) 2010 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 48: 5126- 5134, 2010
Crystalline conjugated polymer containing fused 2,5-di(thiophen-2-yl)thieno[2,3-b]thiophene and thieno[3,4-c]pyrrole-4,6-dione units for bulk heterojunction solar cells
(2011-01-01)
Chen, Guan-Yu
;
Cheng, Yu-Hsin
;
Chou, Yi-Jen
;
Su, Ming-Shin
;
Chen, Chia-Min
A new conjugated polymer, PDTTTPD, comprising 2,5-di-(thiophen-2-yl)thieno[3,2-b]thiophene and thieno[3,4-c]pyrrole-4,6-dione units, exhibits high crystallinity and excellent thermal stability. A device incorporating PDTTTPD and [6,6]-phenyl-C(71)-butyric acid methyl ester (1 : 1, w/w) exhibited a power conversion efficiency of 5.1%.
Crystalline conjugated polymer containing fused 2,5-di(thiophen-2-yl)thieno[2,3-b]thiophene and thieno[3,4-c]pyrrole-4,6-dione units for bulk heterojunction solar cells
(2011-01-01)
Chen, Guan-Yu
;
Cheng, Yu-Hsin
;
Chou, Yi-Jen
;
Su, Ming-Shin
;
Chen, Chia-Min
A new conjugated polymer, PDTTTPD, comprising 2,5-di-(thiophen-2-yl)thieno[3,2-b]thiophene and thieno[3,4-c]pyrrole-4,6-dione units, exhibits high crystallinity and excellent thermal stability. A device incorporating PDTTTPD and [6,6]-phenyl-C(71)-butyric acid methyl ester (1 : 1, w/w) exhibited a power conversion efficiency of 5.1%.
Dual-Output Switched-Capacitor DC-DC Converter With Peseudo-Three-Phase Swap-and-Cross Control and Amplitude Modulation Mechanism
(2013)
Chen, Chia-Min
;
Chiang, Chun-Yen
;
Du, Chen-Cheng
;
Chou, Fang-Ting
;
Hung, Chung-Chih
This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The two outputs were regulated at 2.5 V and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz. The maximal peak-to-peak output ripple voltages for the two outputs under 100 mA load currents were suppressed to below 26 mV and 20 mV, respectively.
Dual-output switched-capacitor DC-DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism
(2018-06-01)
Chen, Chia-Min
;
Su, Chung-Cheng
;
Chou, Fang-Ting
;
Hung, Chung-Chih
;
電機工程學系
This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC-DC converter was implemented in a standard 0.18-mu m 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.
Energy-efficient and cost-effective web API invocations with transfer size reduction for mobile mashup applications
(2014-04-01)
Huang, Chen-Che
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Huang, Jiun-Long
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Tsai, Chin-Liang
;
Wu, Guan-Zhong
;
Chen, Chia-Min
Recently, the proliferation of smartphones and the extensive coverage of wireless networks have enabled numerous mobile users to access Web resources with smartphones. Mobile mashup applications are very attractive to smartphone users due to specialized services and user-friendly GUIs. However, to offer new services through the integration of Web resources via Web API invocations, mobile mashup applications suffer from high energy consumption and long response time. In this paper, we propose a proxy system and two techniques to reduce the size of data transfer, thereby enabling mobile mashup applications to achieve energy-efficient and cost-effective Web API invocations. Specifically, we design an API query language that allows mobile mashup applications to readily specify and obtain desired information by instructing a proxy to filter unnecessary information returned from Web API servers. We also devise an image multi-get module, which results in mobile mashup applications with smaller transfer sizes by combining multiple images and adjusting the quality, scale, or resolution of the images. With the proposed proxy and techniques, a mobile mashup application can rapidly retrieve Web resources via Web API invocations with lower energy consumption due to a smaller number of HTTP requests and responses as well as smaller response bodies. Experimental results show that the proposed proxy system and techniques significantly reduce transfer size, response time, and energy consumption of mobile mashup applications.
Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator
(2013-04-01)
Chen, Chia-Min
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-mu m CMOS technology. With an active area of 0.14 mm(2) (including feedback resistors), the quiescent current is only 40 mu A. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.
Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application
(2013-09-01)
Chen, Chia-Min
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Tsai, Tung-Wei
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Hung, Chung-Chih
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傳播研究所
;
Institute of Communication Studies
This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35-mu m CMOS technology. The device consumes only 25 mu A of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.
Freewheel charge-pump controlled single-inductor multiple-output step-up DC-DC converter
(2013-01-01)
Chen, Chia-Min
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Hsu, Kai-Hsiu
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC-DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 mu H inductor, 4.7 mu F charge-pump capacitors and 33 mu F output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-mu m CMOS process, the proposed circuit occupies 1.3 x 1.3 mm(2). Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for V-O1, V-O2, V-O3 and V-O4, respectively.
New Carbazole-Based Conjugated Polymers Containing Pyridylvinyl Thiophene Units for Polymer Solar Cell Applications: Morphological Stabilization Through Hydrogen Bonding
(2011-02-01)
Hsu, So-Lin
;
Chen, Chia-Min
;
Cheng, Yu-Hsin
;
Wei, Kung-Hwa
;
材料科學與工程學系
We have synthesized two conjugated polymers (P1, P2) containing alternating electron-donating and -accepting units, based on N-alkyl-2,7-carbazole, 4,7-di(thiophen-5-yl)-2,1,3-benzothiadiazole and 3-[2-(4-pyridyl)vinyl]thiophene units. These conjugated polymers contained different contents of pyridine units, which were incorporated to form hydrogen bonds with [6,6]-phenyl-C(61)-butyric acid (PCBA). When these hydrogen bonding interactions were present in the polymer thin films, their thermal stability improved; deterioration, which occurred through aggregation of PCBA methyl ester after lengthy annealing times, was also suppressed. The power conversion efficiency of a device incorporating the film featuring hydrogen bonding interactions remained at 75% of the original value after thermal annealing for 5 h at 140 degrees C. (C) 2010 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 49: 603-611, 2011