Browsing by Author "Chen, Chieh-Yang"

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Capacitance Characteristic Optimization of Germanium MOSFETs with Aluminum Oxide by Using a Semiconductor-Device-Simulation-Based Multi-Objective Evolutionary Algorithm Method
(2015-04-03)
Li, Yiming
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Chen, Chieh-Yang
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傳播研究所
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電機資訊學士班
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Institute of Communication Studies
This paper, for the first time, optimizes the characteristics of capacitance-voltage (C-V) of germanium (Ge) metal-oxide-semiconductor field effect transistors (MOSFETs) with aluminum oxide (Al2O3) by using a semiconductor-device-simulation-based multi-objective evolutionary algorithm (MOEA) technique. By solving a set of 2D semiconductor device transport equations, numerical simulation is intensively performed for the optimization of the C-V curve of Ge MOSFET devices. To optimize the capacitance of Ge MOSFETs with respect to the applied voltage, by minimizing the total errors of the C-V curve between the device simulation and a given specification (and experimentally measured data), the thicknesses of Al2O3 and GeO2, the work function of gate electrodes, the distribution range of channel doping, the dielectric constants of Al2O3 and GeO2, and the source/drain doping concentration are considered in the process of optimization. The semiconductor device simulation and the MOEA method are integrated and performed based on a unified optimization framework. According to the sharp variation characteristics of the C-V curve, except for using a residual sum of squares (RSS) (i.e., the sum of squares of residuals) as an objective function, physical key parts of the curve are also considered in the optimization problem. The engineering results of this study indicate that the semiconductor-device-simulation-based MOEA method shows great performance to optimize the parameters, which not only minimize the objective values but also match the curve shape.
Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits
(2019-05-01)
Li, Yiming
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Chen, Chieh-Yang
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Chuang, Min-Hui
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Chao, Pei-Jung
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電機工程學系
In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal-oxide-semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device's nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device-circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.
Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si:H TFTs Gate Driver Circuit Design Optimization
(2015-01-01)
Hung, Sheng-Chin
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Chen, Chieh-Yang
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Chiang, Chien-Hsueh
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Li, Yiming
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分子醫學與生物工程研究所
In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 mu s and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.
Device Simulation-Based Multiobjective Evolutionary Algorithm for Process Optimization of Semiconductor Solar Cells
(2013-07-03)
Li, Yiming
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Chen, Yu-Yu
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Chen, Chieh-Yang
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Shen, Cheng-Han
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Cheng, Hui-Wen
This article implements for the first time a numerical semiconductor device simulation-based multiobjective evolutionary algorithm (MOEA) for the characteristic optimization of amorphous silicon thin-film solar cells, based upon a unified optimization framework (UOF). To calculate the device's characteristic, a set of coupled solar cell transport equations consisting of the Poisson equation, the electron-hole current continuity equations, and the photo-generation model is solved numerically. Electrical characteristics, the short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated to analyze the properties of the explored solar cells. The aforementioned device simulation results are used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm (NSGA-II) in the UOF. Notably, designing parameters including the material and structural parameters, and the doping concentrations are simultaneously optimized for the explored solar cells. The simulation-based MOEA methodology is useful in optimal structure design and manufacturing of semiconductor solar cells.
Electrical Characteristic and Power Consumption Fluctuations of Trapezoidal Bulk FinFET Devices and Circuits Induced by Random Line Edge Roughness
(2015)
Chen, Chieh-Yang
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Huang, Wen-Tsung
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Li, Yiming
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資訊工程學系
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Department of Computer Science
In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. The resist-LER is most influential on characteristic fluctuation. For the same type, spacer-LER has at least 85 % improvement on sigma V-th compared with resist-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.
Experimentally Effective Clean Process to C-V Characteristic Variation Reduction of HKMG MOS Devices
(2013)
Chen, Chien-Hung
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Li, Yiming
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Chen, Chieh-Yang
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Chen, Yu-Yu
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Hsu, Sheng-Chia
In this work, the planar HKMG MOS devices are fabricated on (100) wafer with p-substrate. To improve the samples\' interface roughness between the Si/Ge film and the interface layer, three different clean treatments are considered to fabricate the MOS devices. Among processes, the experiment indicates that HF and water rinse can present hydrogen termination to bond silicon as a good passivation. The measured C-V curves and HRTEM of the fabricated samples show the interface roughness is improved significantly. The extracted shift of flat band voltage (Delta V-fb) and density of interface traps (D-it) have around 50% improvement.
Lateral amorphous selenium metal-insulator-semiconductor-insulator-metal photodetectors using ultrathin dielectric blocking layers for dark current suppression
(2016-12-21)
Chang, Cheng-Yi
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Pan, Fu-Ming
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Lin, Jian-Siang
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Yu, Tung-Yuan
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Li, Yi-Ming
We fabricated amorphous selenium (a-Se) photodetectors with a lateral metal-insulator-semiconductor-insulator-metal (MISIM) device structure. Thermal aluminum oxide, plasma-enhanced chemical vapor deposited silicon nitride, and thermal atomic layer deposited (ALD) aluminum oxide and hafnium oxide (ALD-HfO2) were used as the electron and hole blocking layers of the MISIM photodetectors for dark current suppression. A reduction in the dark current by three orders of magnitude can be achieved at electric fields between 10 and 30 V/mu m. The effective dark current suppression is primarily ascribed to electric field lowering in the dielectric layers as a result of charge trapping in deep levels. Photogenerated carriers in the a-Se layer can be transported across the blocking layers to the Al electrodes via Fowler-Nordheim tunneling because a high electric field develops in the ultrathin dielectric layers under illumination. Since the a-Se MISIM photodetectors have a very low dark current without significant degradation in the photoresponse, the signal contrast is greatly improved. The MISIM photodetector with the ALD-HfO2 blocking layer has an optimal signal contrast more than 500 times the contrast of the photodetector without a blocking layer at 15 V/mu m. Published by AIP Publishing.
Mobility model extraction for surface roughness of SiGe along (110) and (100) Orientations in HKMG bulk FinFET devices
(2013-09-01)
Chen, Chien-Hung
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Li, Yiming
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Chen, Chieh-Yang
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Chen, Yu-Yu
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Hsu, Sheng-Chia
In this work, the FinFET HKMG MOS devices are fabricated on silicon wafer with p-substrate. The interface roughness between the SiGe and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. (C) 2013 Elsevier B.V. All rights reserved.
Multi-Objective Display Panel Design Optimization using Circuit Simulation-Based Evolutionary Algorithm
(2012)
Chen, Yu-Yu
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Li, Yiming
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Chen, Chieh-Yang
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Chiang, Chien-Hshueh
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傳播研究所
We for the first time implement a multi-objective evolutionary algorithm (MOEA) to optimize the display panel gate driver circuits with amorphous silicon thin-film transistors (ASG driver circuit). The MOEA is integrated with a circuit simulator based upon a unified optimization framework. The results of this study indicate the developed optimization flow can find the better solutions than a simple GA. The measurement data of the fabricated sample further show the achieved result is robust and superior to the original design. This approach benefits design and manufacturing of display panels in the industry of information and communications technology.
On Characteristic Variability of 16-nm-Gate Bulk FinFET Devices Induced by Intrinsic Parameter Fluctuation and Process Variation Effect
(2013-01-01)
Chen, Chieh-Yang
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Li, Yiming
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Chen, Yu-Yu
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Chang, Han-Tung
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Hsu, Sheng-Chia
On Statistical Variation of MOSFETs Induced by Random-Discrete-Dopants and Random-Interface-Traps
(2012)
Li, Yiming
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Su, Hsin-Wen
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Chen, Chieh-Yang
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Cheng, Hui-Wen
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Chen, Yu-Yu
In this work, we statistically study characteristic fluctuation of 16-nm-gate high-kappa/metal gate (HKMG) MOSFETs by random-discrete-dopants (RDDs) inside silicon channel and random-interface-traps (RITs) at high-kappa/silicon interface. Randomly generated devices with three-dimensional (3D) RDDs inside device channel and 2D RITs at HfO2/Si interface are incorporated into quantum mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to RITs near the source and drain ends, and RDDs near the device channel surface and silicon substrate. Characteristic fluctuations are affected to different extents by the random combinatorial RDDs and RITs. Nonlinearly correlated RDDs and RITs further violate the statistical assumption of independent identical distributions between the RDDs- and RITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is less than their statistical sum due to local interaction of surface potentials resulting from the RDDs and RITs simultaneously. In contrast to RDDs fluctuation, the screening effect of device\'s inversion layer cannot effectively screen potential\'s variation resulting from RITs; thus, devices still have noticeable gate capacitance characteristic fluctuation under high gate bias.
Photoconductive properties of polycrystalline selenium based lateral MISIM photodetectors of high quantum efficiency using different dielectrics as the charge blocking layer
(2019-07-01)
Chang, Cheng-Yi
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Huang, Yu-Wei
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Lin, Yi-Jie
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Liao, Jye-Yow
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Lin, Jian-Siang
We studied the photoconductive performance of polycrystalline selenium (pc-Se) based photodetectors with a lateral metal-insulator-semiconductor-insulator-metal (MISIM) device structure. The insulator layer is a 10 nm-thick Ga2O3, HfO2, or Al2O3 thin film, and used as a charge blocking layer (CBL) to suppress dark current injected from the Al electrodes. The dark current suppression primarily depends on the barrier height of the junctions between the CBLs and electrodes. The Ga2O3 CBL exhibits a poor dark current suppression compared to the HfO2 and the Al2O3 CBLs because of a lower electron barrier at the cathode. The lateral pc-Se photodetectors exhibit a very high internal photocurrent gain due to Fowler-Nordheim tunneling at relatively low applied voltages. The better crystallinity of pc-Se grains formed on the Ga2O3 CBL leads to a higher photoconversion efficiency for the MISIM-Ga2O3 photodetector. Compared with amorphous Se based lateral MISIM photodetectors, the pc-Se photodetectors demonstrate a uniform and much better photoconductive performance over the visible spectrum.
Process Variation Effect, Metal-Gate Work-Function Fluctuation and Random Dopant Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFET Devices
(2015)
Li, Yiming
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Chang, Han-Tung
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Lai, Chun-Ning
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Chao, Pei-Jung
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Chen, Chieh-Yang
In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-kappa/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.
Random Work Function Induced DC Characteristic Fluctuation in 16-nm High-kappa/Metal Gate Bulk and SOI FinFETs
(2012)
Su, Hsin-Wen
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Chen, Yu-Yu
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Chen, Chieh-Yang
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Cheng, Hui-Wen
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Chang, Han-Tung
This work studies the metal gate\'s work function fluctuation induced DC characteristic fluctuation in the 16-nm bulk and silicon-on-insulator (SOI) fm-type field effect transistor (FinFET) devices using an experimentally calibrated 3D device simulation. The method of localized work function fluctuation simulation enables us to estimate local fluctuations including the nanosized grain\'s random effects of FinFET with TiN/HfO2 gate stacks. The result of this study shows characteristic fluctuation strongly depends upon the size of localized nanosized metal grains. The shape of grains does have marginal influence on device\'s variability.
Random-work-function-induced characteristic fluctuation in 16-nm-gate bulk and SOI FinFETs
(2014-01-01)
Li, Yiming
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Chen, Chieh-Yang
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Chen, Yu-Yu
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資訊工程學系
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Department of Computer Science
In this paper, we, for the first time, study the metal gate\'s work-function-fluctuation-induced variability in the 16-nm-gate bulk and silicon on insulator (SOI) fin-type field effect transistor (FinFET) devices using an experimentally calibrated 3D device simulation. According to metal\'s property, random nanosized grains of titanium nitride (TiN) gate are statistically positioned in the gate region to examine the associated electrostatic potential and carrier transportation characteristics, concurrently capturing fluctuations resulting from nanosized grain\'s random number, position and size effects. The newly advanced methodology of localised work function fluctuation simulation enables us to estimate characteristic fluctuations and to examine the nanosized grain\'s random effects for the 16-nm-gate bulk and SOI FinFETs with TiN/HfO2 gate stacks with respect to the aspect ratio (AR = fin height/fin width) of two. The results of this study show that the DC characteristic fluctuation of FinFET devices strongly depends on the high and low work functions of localised nanosized metal grains. The threshold voltage (V-th) varies with the number of grain sizes and the V-th\'s fluctuation (sigma V-th) is suppressed as the grain size is minimised. sigma V-th of SOI FinFET (about 9.7 mV) is about 1.5 times smaller than that with bulk FinFET (about 14.6 mV). Furthermore, sigma V-th of SOI FinFET with minimal metal grain\'s size of 2 x 2 nm(2) can be reduced about 23%, compared with the result of bulk one.
Statistical Device Simulation of Characteristic Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFETs Induced by Various Discrete Random Dopants
(2016)
Sung, Wen-Li
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Chang, Han-Tung
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Chen, Chieh-Yang
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Chao, Pei-Jung
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Li, Yiming
We study the impact of random dopant fluctuation (RDF) on electrical characteristics of 10-nm-gatehigh kappa/metal gate gate-all-around silicon nanowire MOSFET devices. To provide the best accuracy of device simulation, model parameters are validated by using full quantum mechanical simulation and calibrated with experimental results. Physical mechanism of RDs inside channel and penetration from the source/drain extensions into the channel is discussed. Electrical characteristic of the device is estimated with respect to different types of RDF.
Statistical Device Simulation of Intrinsic Parameter Fluctuation in 16-nm-Gate N- and P-type Bulk FinFETs
(2013-01-01)
Chen, Yu-Yu
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Huang, Wen-Tsung
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Hsu, Sheng-Chia
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Chang, Han-Tung
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Chen, Chieh-Yang
In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-kappa / metal gate n- and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations\' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.
Upper/lower-side random dopant fluctuation on 16-nm-gate HKMG bulk FinFET
(2015-01-01)
Li, Yiming
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Huang, Wen-Tsung
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Chen, Chieh-Yang
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Chen, Yu-Yu
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資訊工程學系
In this work, we for the first time classify dopants that exist near the source/drain side or the upper/lower side of silicon fin and explore the impact of random dopants\' (RDs) position on devices\' DC characteristic. The effects of random dopant fluctuation (RDF) on the performance of 16-nm-gate HKMG bulk FinFET are studied by using experimentally validated three-dimensional RDF device simulation. The dopants near the source side or the upper fin would induce large barrier for electrons, so the threshold voltage (Vth) will be increased in n-type HKMG bulk FinFET devices which have more dopants on the source side or the upper fin. In addition, the upper-fin\'s dopants are discovered to have larger influence on the profile of energy band. Moreover, the issue about Vth\'s fluctuation on both the planar MOSFET and the bulk FinFETs with different aspect ratios (AR) is studied. The higher-AR HKMG bulk FinFET devices have relatively smaller Vth\'s variation induced by RDF.
Work Function Modulation of Monolayer MoS2 Doped with 3d Transition Metals
(2017-01-01)
Tsai, Yi-Chia
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Chen, Chieh-Yang
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Ho, Min-Shao
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Li, Yiming
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電機工程學系