Browsing by Author "Chen, Chien-Ju"

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1.7 to 2.3 Gbps OOK LED VLC Transmission Based on 4 x 4 Color-Polarization-Multiplexing at Extremely Low Illumination
(2019-08-01)
Yeh, Chien-Hung
;
Weng, Jui-Hung
;
Chow, Chi-Wai
;
Luo, Chien-Ming
;
Xie, Yue-Ru
To achieve the high traffic rate of a GaN LED-based visible light communication (VLC), a 4 x 4 color-polarization-multiplexing system is demonstrated by using two blue and two green LEDs. In the measurement, an available bandwidth of blue and green LEDs can be greater than 465 MHz for VLC modulation traffic by using the suitable analogy front end circuit. Hence, the proposed VLC system can deliver 1.7 to 2.3 Gbit/s ON-OFF keying traffic rates in the free space transmission length of 1-4 m under the extremely low illumination of 6.9-136.1 lux for the indoor application. Moreover, the measured BER of each LED is less than the forward error correction target of 3.8 x 10(-3) to maintain the better signal performance.
Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices
(2015)
Wu, Tse-Ching
;
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the hybrid TFET-FinFET 32-bit carry-look-ahead adder (CLA) circuit and compare the delay, power and power-delay product (PDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. In the hybrid design, TFETs are used for the top critical path to reduce the longest path delay, and FinFETs are used for the rest of the circuit to reduce switching power and leakage power. The PDP of the hybrid TFET-FinFET CLA circuit is better than the circuits with all FinFET and all TFET implementations in the vicinity of V-DD=0.3V. However, as the operating voltage is further reduced, the lower-ranked critical paths (e.g. 2nd critical path) with some FinFET devices in the path stick out, and the delay and PDP become inferior to all TFET implementation.
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
(2015)
Wu, Tse-Ching
;
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage (CMOS)-M-2 latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.
Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness
(2015)
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we comprehensively investigate the impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-look-ahead adder (CLA) circuits operating in near-threshold region using atomistic 3D TCAD mixed-mode simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that at low operating voltage (<0.3V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET even with the impacts of random variations. As the operating voltage decreases, the performance advantage of TFET CLA becomes more significant due to its better I-on and C-g,C-ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse I-off variability of TFET devices.
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
(2014)
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on ION and IOFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.