Browsing by Author "Chen, Hung-Cheng"

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Fast Intra Prediction Algorithm and Design for High Efficiency Video Coding
(2016)
Fang, Han-Chiou
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Chen, Hung-Cheng
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To meet the real time demand of HEVC intra encoding, this paper proposed a fast intra prediction algorithm and its design with a gradient weight controlled block size selection to reduce number of PU (prediction unit) sizes to two. These two PU sizes will be further selectively reduced to one based on its SATD distribution. The simulation results show that the proposed algorithm can save 79% encoding time for all-intra main case compared to HM-9.0rc1, with 3.4% BD-rate increase. The hardware design costs 224K gate count and 1.7KB SRAM for 4Kx2k@30fps processing with TSMC 90 nm CMOS technology when operated at 270 MHz operating frequency.
Fast Rate Distortion Optimization With Adaptive Context Group Modeling For HEVC
(2017-01-01)
Chen, Hung-Cheng
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Rate distortion optimization helps decide the best coding mode and partition to improve coding efficiency, but suffers from serious data dependency and complexity that hinders an efficient hardware encoder implementation. Thus, this paper presents a hardware-friendly fast rate-distortion method and its design. For rate estimation, we propose a context group adaptive entropy based method for more precise estimation and parallel computation that is applied to both intra and inter predictions instead of intra prediction only as in previous approaches. For distortion estimation, we use the transform domain instead of spatial domain computation to save inverse discrete transform computation and image reconstruction, and reduce cost further by adopting fixed zero sub-blocks in the high frequency part for 32x32 and 16x16 blocks. The simulation results shows 1.77% BD rate loss in average. The proposed hardware design adopts the interleaved Luma/Chroma coding schedule to improve hardware utilization. The final implementation with TSMC 40nm CMOS process can achieve real time 4Kx2K@30fps encoding with 57.95K gate count while operating under 400MHz clock frequency.