Fast Intra Prediction Algorithm and Design for High Efficiency Video Coding

Abstract

To meet the real time demand of HEVC intra encoding, this paper proposed a fast intra prediction algorithm and its design with a gradient weight controlled block size selection to reduce number of PU (prediction unit) sizes to two. These two PU sizes will be further selectively reduced to one based on its SATD distribution. The simulation results show that the proposed algorithm can save 79% encoding time for all-intra main case compared to HM-9.0rc1, with 3.4% BD-rate increase. The hardware design costs 224K gate count and 1.7KB SRAM for 4Kx2k@30fps processing with TSMC 90 nm CMOS technology when operated at 270 MHz operating frequency.