Browsing by Author "Chen, Jian-Hao"

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A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation
(2008)
Wu, Woei-Chemg
;
Lai, Chao-Sung
;
Lee, Shih-Ching
;
Ma, Ming-Wen
;
Chao, Tien-Sheng
In this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
Highly reliable multilevel and 2-bit/cell operation of wrapped select gate (WSG) SONOS memory
(2007-03-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (> 150 degrees C) and good endurance (> 10(4)) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application.
Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
(2008-01-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Chen, Jian-Hao
In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V(TH) distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.
Si nanocrystal memory devices self-assembled by in situ rapid thermal annealing of ultrathin a-Si on SiO2
(2007)
Chen, Jian-Hao
;
Lei, Tan-Fu
;
Landheer, Dolf
;
Wu, Xiaohua
;
Liu, Jian
Si-nanocrystal memories have been fabricated using the thermal agglomeration of an ultrathin (0.9-3.5 nm) amorphous Si (a-Si) film. The a-Si was deposited by electron beam evaporation followed by in situ annealing at 850 C for 5 min. Hemispherical nanocrystals were obtained with a dot density up to 3.9 x 10(11) cm(-2), and a stored charge density of 4.1 x 10(12) cm(-2) (electron + hole) was achieved. The data retention characteristics of nanocrystal-embedded devices have shown a 1 V memory window after 100 h. Well-separated Si nanocrystals with a 23-32% surface-coverage ratio have been successfully demonstrated. The process compatibility of the proposed technique was also discussed. (C) 2007 The Electrochemical Society.
Soft Partitioning Flow Tables for Virtual Networking in Multi-Tenant Software Defined Networks
(2018-03-01)
Lin, Ying-Dar
;
Liu, Te-Lung
;
Chen, Jian-Hao
;
Lai, Yuan-Cheng
;
資訊工程學系
In a multi-tenancy software defined network (SDN) environment, physical devices such as switches are shared among tenants. In addition to a centralized controller, each tenant has his own controller that manages resources allocated to the tenant. Hence, the centralized controller performs SDN resource virtualization among tenants and acts as proxy between physical resources and tenant controllers. In order to manage the flow tables of the SDN switches, two partitioning strategies are considered. Hard partitioning of flow tables allocates a fixed amount of flow entries to each tenant, but flow tables are wasted if the tenant does not actually use them. On the other hand, soft partitioning strategy shares available flow entries among tenants, resulting in higher utilization but a resource monopoly problem, i.e., flow entries dominated by some greedy tenants. To achieve high flow table utilization and avoid the resource monopoly problem, we propose a soft-partitioning resource manager (SPRM) to manage the flow table resources in a multi-tenancy SDN environment. In SPRM, the allowed number of flow entries for each tenant ranges from a lower bound which equals to the tenant's quota to an upper bound which is dynamically adjusted according to the tenant's past usage. If an incoming flow request of a tenant is beyond his lower bound but under his upper bound, it could be temporarily accepted when there are free entries available. These borrowed flow entries will later be replaced if needed. If a request of a tenant is beyond his upper bound, SPRM will select a least-recently used flow entry of the tenant and replace it with the new request. In addition, SPRM monitors flow table resources and submits modify flow entry messages directly to SDN switches without checks by the management plane as possible in order to reduce flow modification latency. As a result, SPRM could reach higher flow table utilization and lower both flow entry miss rate and Packet_in events. Experimental results show that 100% flow rejections, and 95% Packet_in events are reduced while flow modification latency is decreased by 30%, as compared to hard partitioning.
X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO(3) high-k dielectric prepared by sol-gel spin coating method
(2008-09-01)
Kao, Kuo-Hsing
;
Chuang, Shiow-Huey
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chen, Jian-Hao
The characteristics of CoTiO(3) high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k similar to 40.2) of CoTiO(3) dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO(2) and spin-on CoTiO(3) was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO(2) and spin-on CoTiO(3) were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO(3) directly with SiO(2) and indirectly with Si was determined in this work. (c) 2008 American Institute of Physics.
X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method
(2008-09-01)
Kao, Kuo-Hsing
;
Chuang, Shiow-Huey
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chen, Jian-Hao
The characteristics of CoTiO3 high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k similar to 40.2) of CoTiO3 dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO2 and spin-on CoTiO3 was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO2 and spin-on CoTiO3 were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO3 directly with SiO2 and indirectly with Si was determined in this work. (c) 2008 American Institute of Physics.