Browsing by Author "Chen, Ke-Horng"

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0.65V-Input-Voltage 0.6V-Output-Voltage 30ppm/degrees C Low-Dropout Regulator with Embedded Voltage Reference for Low-Power Biomedical Systems
(2014-01-01)
Chen, Wei-Chung
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Su, Yi-Ping
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Lee, Yu-Huei
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Wey, Chin-Long
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Chen, Ke-Horng
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
(2015-06-01)
Lai, Shin-Chi
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Liu, Chih-Hao
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Wang, Ling-Yi
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Chen, Shin-Hao
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Chen, Ke-Horng
This paper presents a novel algorithm and architecture design for 18-band quasi-class-2 ANSI S1.11 1/3 octave filterbank. The proposed design has several advantages such as lower group delay, lower computational complexity, and lower matching error. The technique we developed in this paper can be summarized as follows: 1) a simple low-pass filter (LPF) and discrete cosine transform (DCT) modulation are utilized to generate a uniform 9-band filterbank first, and then all elements of are replaced by all-pass filters to obtain a non-uniform filterbank; 2) a fast recursive structure and variable-length algorithm is further developed to efficiently accomplish DCT modulation. Thus, the spectrum of LPF can be easily spanned and flexibly extended to the location of the desired central frequency; 3) after employing the multi-rate algorithm, an 18-band non-uniform filterbank is generated from two 9-band sub filterbanks by following the proposed design steps and parameter determinations. Compared with the latest Liu et al.\'s quasi-class-2 ANSI S1.11 design, the proposed method-I (Proposed-I) totally has 72.8% reduction for multiplications per sample, 11.25-ms group delay, and 59 additions decreased per sample. Moreover, the maximum matching error of the proposed method-II (Proposed-II) is averagely equal to 1.79 dB much smaller than that of the latest Wei et al.\'s design. For the proposed variable-length DCT modulation, only 2 adders, 2 multipliers, 2 multiplexers, and 5 registers are required for hardware implementation after applying VLSI retiming scheme. Overall, the proposed filterbank design would be a new solution for future applications in the area of hearing aids.
120% Harvesting Energy Improvement by Maximum Power Extracting Control for High Sustainability Magnetic Power Monitoring and Harvesting System
(2015-04-01)
Huang, Tzu-Chi
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Du, Ming-Jhe
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Kang, Yu-Chai
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Peng, Ruei-Hong
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Chen, Ke-Horng
The magnetic energy harvesting (MEH) circuit and the power monitoring system are proposed in this paper to enlarge the system sustainability on wireless sensing or the monitoring system. The proposed MEH circuit harvests magnetic power on power wires through a power sensing current transformer (CT) and charges power monitoring system. The MEH circuit includes the direct ac-dc rectifier and the maximum power extracting (MPE) control circuit. The direct ac-dc rectifier can directly rectify ac input to the dc output current. The proposed MPE control fits the characteristic of magnetic energy source compared to the conventional resistor emulation maximum power point tracking method. Owing to continuous tracking the maximum power of the CT, 120% harvesting power improvement can be achieved under the same CT\'s sensing current. Peak efficiency of 82% can be achieved under the sensing current of 8 A. The test chip is fabricated in 0.25 mu m CMOS process with an active area of 0.98 mm(2).
120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
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Chen, Jui-Lung
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Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
200nA Low Quiescent Current Deep-Standby Mode in 28nm DC-DC Buck Converter for Active Implantable Medical Devices
(2015)
Chu, Li-Cheng
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Yang, Te-Fu
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Huang, Ru-Yu
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Su, Yi-Ping
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Lin, Chiun-He
the proposed deep-standby mode (DSM) is used in 28nm power management unit (PMU) for long-term usage in active implantable medical devices (AIMD). The PMU can upgrade its normal mode with the proposed embedded auto-cancellation (EAC) technique in order to have high accuracy even if the battery is aging and the PVT variations occur. The test chip fabricated in 28nm CMOS process features low quiescent current of 200nA and output voltage accuracy of 98%. Seamless transition among the DSM and the accurate mode demonstrates both low quiescent current and high accuracy can be achieved in the proposed PMU.
800V Ultra-High-Voltage Start-up Mechanism for Pre-regulator in Power Factor Correction (PFC) Controller
(2011)
Chen, Chi-Lin
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Tsai, Jen-Chieh
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Chen, Yi-Ting
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Ni, Chia-Lung
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Chen, Chun-Yen
The on-chip 800V ultra-high-voltage (UHV) start-up mechanism was introduced in this paper. Using the UHV start-up mechanism can minimize the current leakage at the AC input and remove the need of external start-up resistor and capacitor. As a result, the standby current can be decreased to improve the efficiency of AC-DC systems. Furthermore, the zero current detection (ZCD) circuit was used here to ensure the work of the pre-regulator. An inductance coil will detect the primary inductance current and reflect the voltage, which is detected by ZCD circuit to provide the energy to the pre-regulator. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Certainly, high efficiency of 95% can be ensured at the output power of 50W.
87% Overall High Efficiency and 11 mu A Ultra-Low Standby Current Derived by Overall Power Management in Laptops With Flexible Voltage Scaling and Dynamic Voltage Scaling Techniques
(2016-04-01)
Yang, Shang-Hsien
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Chen-Min
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Meng, Che-Hao
The proposed overall power management in laptops can improve overall power conversion efficiency by the flexible voltage scaling (FVS) technique in cooperation with conventional dynamic voltage scaling (DVS) technique. The FVS technique separates the controller into two parts. One is a simple primary side controller and the other is emerged into the power management unit in the laptop for getting direct power control from the microprocessor. 12% light load efficiency and 7% peak efficiency are improved compared to conventional design with the DVS technique only but without the FVS technique. Furthermore, green mode is proposed to effectively reduce chip quiescent current to 11 mu A and to suppress power loss to 10 m W in ultra-light load, which is much smaller than 500 mW standby power defined by the restriction of Energy Star Standard and 40 mW of state-of-art commercial products.
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
(2015-01-01)
Su, Yi-Ping
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Lin, Chiun-He
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Peng, Shen-Yu
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Huang, Ru-Yu
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Yang, Te-Fu
92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques
(2013-11-01)
Su, Yi-Ping
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Chen, Chun-Yen
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Ni, Chia-Lung
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Kang, Yu-Chai
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Chen, Yi-Ting
This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.
93% Efficiency and 0.99 Power Factor in Pseudo-linear LED Driver
(2016-01-01)
Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Chuang, Kai-Cheng
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Yang, Wen-Hau
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Chen, Ke-Horng
The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5 mu m 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.
94% Performance Improvement by Time-shift Control (TSC) Technique in Cloud Computing Voltage Regulator Module (VRM)
(2013)
Meng, Che-Hao
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Su, Yi-Ping
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Huang, Yu-Ping
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Lee, Yu-Huei
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Chen, Ke-Horng
the time-shift control (TSC) technique for voltage regulator module (VRM) is proposed to achieve high performance power supply for servers in cloud computing. Four power stages are adopted to provide high current driving capability and low output ripple. Besides, the power request, which includes the number of active phases and voltage identification (VID), is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSC technique improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. Besides, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSC.
95% Light-load Efficiency Single-Inductor Dual-Output DC-DC Buck Converter with Synthesized Waveform Control Technique for USB Type-C
(2016)
Yang, Wen-Hau
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Lin, Chiun-He
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 520V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400 mu m*1350 mu m.
99% High Accuracy Knee Voltage Detection for Primary-side Control in Flyback Converter
(2015)
Tsai, Tsung-Hsun
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Chen, Ke-Horng
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Tsai, Tsung-Yen
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Lin, Jian-Ru
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Lin, Ying-Hsi
this paper proposed the adaptive knee voltage detection (KVD) technique to improve the output voltage accuracy of the primary side regulator. Owing to the insertion of the snubber circuit for reducing overshoot voltage, conventional KVD technique fails to get the output voltage information and thus to deteriorate the output voltage accuracy. Analysis of the snubber circuit and the resonance of the primary side can determine the band-pass filter in the proposed AKVD technique to get high accuracy output information without being affected by any kinds of resonances. Test chip designed in VIS 0.5 mu m BCD process demonstrates the accuracy of the output voltage higher than 99%. Besides, any abnormal detection won\'t happen and thus the output ripple can be kept low.
99.4% Peak Audio Signal Recovery Rate and Ultra-Low 0.32dB Matching Error with 10Hz High Resolution Filter Fitting Wearable Aided Speech Compensation System
(2015)
Lin, Yen-Ting
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Lai, Shin-Chi
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Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
to get high sound quality, the proposed adaptive speech compensation (ASC) system fits psychoacoustic curves for individual needs. Moreover, characteristics of the speakers are considered by real-time speaker impedance estimation (RT-SIE) technique. Hence, original signal can be restored for every user with any speakers. ASC system has 99.4% peak original signal recovery rate by predicting and controlling output signal precisely. And the built-in 10Hz high resolution acoustic filter fitting scheme (AFFS) has less than 0.32dB matching error with an over 80dB hearing loss.
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
(2015-01-01)
Chiu, Chao-Chang
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Huang, Po-Hsien
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Lin, Moris
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Chen, Ke-Horng
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Lin, Ying-Hsi
The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
A 1-V, 16.9 ppm/degrees C, 250 nA Switched-Capacitor CMOS Voltage Reference
(2011-04-01)
Hsieh, Chun-Yu
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Huang, Hong-Wei
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Chen, Ke-Horng
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電控工程研究所
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Institute of Electrical and Control Engineering
An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35-mu m CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5V N-type transistors to operate in the saturation and subthreshold regions, respectively. In place of resistors, a precise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the temperature is 80 degrees C, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is -41 dB at 100 Hz and -17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm(2).
A 100W and 91% GaN-Based Class-E Wireless-Power-Transfer Transmitter with Differential-Impedance-Matching Control for Charging Multiple Devices
(2019-01-01)
Xie, Cheng-Yu
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Yang, Shang-Hsien
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Lu, Shen-Fu
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Lin, Fa-Yi
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Lin, Yen-An
A 2.5W Tablet Speaker Delivering 3.2W Pseudo High Power by Psychoacoustic Model Based Adaptive Power Management System
(2014)
Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
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Lai, Shin-Chi
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Kang, Sheng
for a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a +/- 4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.
A 20MHz Low Dropout Controlled Current Sensor for Constant On-Time Based Envelop Tacking Supply Modulator for Radio Frequency Power Amplifier
(2018-01-01)
Lin, Wei-Ting
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Lin, Zong-Yi
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Liu, Chia-Hao
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Chen, Ke-Horng
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Lin, Ying-Hsi
this paper presents a LDO-controlled current sensor for accelerating constant on-time (COT) switching regulators (SWRs) for high efficiency envelope tracking power modulators (ETSMs) for RF power amplifiers (RF PAs). The proposed LDO-controlled current sensor controls the feedback loop of the SWR, rather than the traditional current sensing technique, in the case of fast envelope tracking. The LDO regulator behaves as the master to rapidly trigger the SWR as a slave energy provider to rapidly deliver the average energy to the RF PA for high efficiency. The experimental results show that the test chip fabricated in 0.18 mu m CMOS process can accurately track the RF envelope signal, and the peak efficiency is 86.7% when the power is 0.95W.
A 20MS/s Buck/Boost Supply Modulator for Envelope Tracking Applications with Direct Digital Interface
(2014)
Yang, Shang-Hsien
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Wey, Chin-Long
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Chen, Jing-Jia
a buck/boost supply modulator (BBSM) is proposed for 4G LTE RF power amplifier (RF-PA) envelope tracking applications. The H-bridges used in non-inverting buck/boost converters are metamorphosed into the current sources and switches of a 4-bit current-steering DAC-like supply modulator. Fast tracking speed is achieved through its inherent open-loop topology, while the direct digital interface provides easy control and integration with digital LTE baseband SoCs. The proposed BBSM is capable of delivering peak power of 2.8W at 20MS/s, with a peak efficiency of 75 %.