Browsing by Author "Chen, Kuo-Hua"

Now showing 1 - 13 of 13

2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
;
Chou, Lei-Chun
;
Huang, Teng-Chieh
;
Wu, Shang-Lin
;
Wang, Tang-Shuan
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
(2015-02-01)
Chang, Chih-Wei
;
Chou, Lei-Chun
;
Huang, Po-Tsang
;
Wu, Shang-Lin
;
Lee, Shih-Wei
We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.
A TSV-Based Bio-Signal Package With mu-Probe Array
(2014-02-01)
Chou, Lei-Chun
;
Lee, Shih-Wei
;
Huang, Po-Tsang
;
Chang, Chih-Wei
;
Chiang, Cheng-Hao
Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.
A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array
(2014-01-01)
Chou, Lei-Chun
;
Lee, Shih-Wei
;
Cheng, Chuan-An
;
Huang, Po-Tsang
;
Chang, Chih-Wei
Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
(2013)
Huang, Teng-Chieh
;
Huang, Po-Tsang
;
Wu, Shang-Lin
;
Chen, Kuan-Neng
;
Chiou, Jin-Chern
In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18 mu m CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6 mu W power consumption and 0.032-mm(2) area. The FoM of this ADC is 49.4fJ/conversion-step.
Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Applications
(2014-01-01)
Wang, Tang-Hsuan
;
Huang, Po-Tsang
;
Chen, Kuan-Neng
;
Chiou, Jin-Chem
;
Chen, Kuo-Hua
Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, an energy-efficient configurable lifting-based discrete wavelet transform (DWT) is proposed for a high-density neural sensing microsystems to extract the features of neural signals by filtering the signals into different frequency bands. Based on the lifting-based DWT algorithm, the area and power consumption can be reduced by decreasing the computation circuits. Additionally, both the time window and mother wavelets can be adjusted via the configurable datapth. Moreover, the power-gating and clock-gating techniques are utilized to further reduce the energy consumption for the energy-limited bio-systems. The proposed configurable DWT is designed and implemented using TSMC 65nm CMOS low power process with total area of 0.11 mm(2) and power consumption of 26 mu W. Moreover, this proposed DWT is also implemented in Lattice MachXO2-1200 FPGA and integrated in a 2.5D heterogeneously integrated high-density neural-sensing microsystem with the power consumption of 211.2 mu W.
Energy-Efficient Low-Noise 16-Channel Analog-Front-End Circuit for Bio-potential Acquisition
(2014-01-01)
Wu, Shang-Lin
;
Huang, Po-Tsang
;
Huang, Teng-Chieh
;
Chen, Kuan-Neng
;
Chiou, Jin-Chern
In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input G(m)-stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18 mu m CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67 mu W for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826 mu V-rms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.
Integrated Microprobe Array and CMOS MEMS by TSV Technology for Bio- Signal Recording Application
(2014-01-01)
Chou, Lei-Chun
;
Lee, Shih-Wei
;
Huang, Po-Tsang
;
Chang, Chih-Wei
;
Wu, Shang-Lin
Bio-signal probes that provide stable observation with high-quality signals are crucial for understanding how the brain works and how the neural signal transmits. Because bio-signals are weak and noisy, the length of the string connecting the sensor and Complementary Metal-Oxide-Semiconductor (CMOS) circuit significantly impacts biosignal quality. The collected weak signals from the sensor must pass through a series of interconnections and interfaces that introduce noise and lead to bulky packaged systems. This work uses through-silicon via (TSV) technology to connect the mu-probe array bio-sensor and CMOS circuit located on opposite sides of a chip for brain neural sensing applications. With the elimination of wire bonding and the reduction of the soldering, bio-signal quality can be significantly improved.
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
(2012)
Chiang, Cheng-Hao
;
Hu, Yu-Chen
;
Chen, Kuo-Hua
;
Chiu, Chi-Tsung
;
Chuang, Ching-Te
Bosch reactive ion etching is widely used for TSV formation. The micro-masking formed during etching can be successfully removed by adjusting the internal parameters during etching. The smooth high-aspect-ratio TSVs were further developed in wafer-level fabrication. Finally, a two-step etching process was developed to achieve tapered TSVs for the following Cu plating process.
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
(2012)
Hu, Yu-Chen
;
Chiang, Cheng-Hao
;
Chen, Kuo-Hua
;
Chiu, Chi-Tsung
;
Chuang, Ching-Te
In this paper, a detailed examination on TSV and cavity inductive coupled plasma (ICP) etching is presented. We investigated the relation such as etching loop number, TSV etching depth and etching rate. Due to particles knocked off from the hard mask and then fallen down to the TSV and cavity bottom, micro-masking issue becomes serious after ICP etching. In addition, parameters of isotropic etching, pressure, and RF bias were studied to investigate the process of micro-masking removal.
Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle
(2014)
Lee, Shih-Wei
;
Shih, Jian-Yu
;
Chuang, Ching-Te
;
Hwang, Wei
;
Chiou, Jin-Chern
In this research, a novel process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. The corresponding structure shows great manufacturability to replace traditional fabrication approach. In addition, Kelvin structure of the daisy chain is designed for evaluating electrical performance and reliability. Moreover, daisy chain with dummy TSV is designed to verify the impact of TSV pitch on TSV fabrication by using electrical measurement. The reliability tests include thermal cycling and humidity test to verify the quality of proposed polymer TSV design. Finally, a void-free polymer TSV with uniform liner formation is successfully fabricated and demonstrated.
Polymer-Based Liner TSV Fabrication Scheme and Its Resistance Variation
(2017-07-01)
Lee, Shih-Wei
;
Shih, Jian-Yu
;
Chen, Kuo-Hua
;
Chiu, Chi-Tsung
;
Chen, Kuan-Neng
In this paper, a process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. By using ring trench etching and BCB deposition in a vacuum environment, uniform BCB liner can be successfully fabricated. Electrical measurement by using Kelvin structure is completed to ensure the performance of fabrication. However, a new phenomenon causing tiny resistance changes with the arrangement of TSV is discovered during the measurement of TSV chain. In this research, this effect is discussed in detail by designing different design of experiment (DOE) to pursue good electrical connection and reduce the variance of delay property of each TSV. Based on statistical results, impacts of TSV manufacturing process variance are discussed and the guideline in high density TSV design is found.
Through-Silicon-Via-Based Double-Side Integrated Microsystem for Neural Sensing Applications
(2013-01-01)
Chang, Chih-Wei
;
Huang, Po-Tsang
;
Chou, Lei-Chun
;
Wu, Shang-Lin
;
Lee, Shih-Wei