Browsing by Author "Chen, LP"

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A macro model of silicon spiral inductor
(2002-05-01)
Su, CY
;
Chen, LP
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Chang, SJ
;
Tseng, BM
;
Lin, DC
A new automatic parameter extraction method for modeling Of silicon Spiral inductors is presented. The Concepts on self-resonance frequency (f(sr)) and quality factor of a spiral inductor are utilized to develop the concise extraction procedures. In the mean time, the presented extraction procedures are programmed as a macro to execute all the extractions automatically and shorten the extraction time effectively. Without any additional optimization or curve fitting, almost all the patterns of S-parameters between the measured and the simulation of extracted data implemented with the extraction macro are less than 5%. The programmed extraction macro makes it fast and accurate to extract and characterize the behaviours or silicon-based spiral inductors with different structures and substrate resistivities. It provides a concrete foundation commercial silicon radiofrequency (RF) Circuit design to realizing on-chip silicon RF integrated circuits. Furthermore, the directly extracted equivalent model parameters, without an optimization, also provide a rule to fairly, effectively and phsically judge the performance of a spiral inductor. (C) 2002 Elsevier Science Ltd. All rights reserved.
A novel technology to reduce the antenna charging effects during polysilicon gate electron-cyclotron-resonance etching
(1996-07-01)
Cheng, HC
;
Kang, TK
;
Ku, TK
;
Dai, BT
;
Chen, LP
A novel technique, which uses Cl-2/O-2 mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl-2/O-2 can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E(bd) degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl-2/O-2 mixed gas.
An automatic macro program for radio frequency MOSFET characteristics analysis
(2001-10-01)
Su, CY
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Chang, SJ
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Chen, LP
;
Ho, YP
;
Huang, GW
The parameter extraction language (PEL) in Agilent IC-CAP software is used to develop an automatic macro program for the analysis of the characteristics of RF MOSFETs. By using this powerful macro program, the time spent on the measurement of the MOSFET characteristics and the related analysis is effectively reduced. This macro program permits a fast and accurate method to obtain the DC and RF characteristics of MOSFETs with different device geometries and operating conditions. It is also suitable for high volume measurements and analyses of MOSFET, and provides a solid jou 71 dation for RF circuit design.
Antenna charging effects on the electrical characteristics of polysilicon gate during electron cyclotron resonance etching
(1996-02-01)
Kang, TK
;
Ueng, SY
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Dai, BT
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Chen, LP
;
Cheng, HC
The nonuniformity of the induced leakage current in metal oxide semiconductor (MOS) capacitors has been investigated in an electron cyclotron resonance (ECR) system. For plasma-etched MOS capacitors with 5-nm-thick oxides, it is found that the leakage currents induced by plasma etching increase with increasing overetching time. However, additional E(bd) (breakdown held) degradation is not obvious as overetching percentage increases from 10% to 50%. A mechanism based on the antenna charging effect has been proposed to explain the E(bd) electrical characteristics. In accordance with the mechanism, the E(bd) degradation has been significantly reduced by first etching off a narrow peripheral edge around the gate pattern.
CMOS RFIC: Application to wireless transceiver design
(2000-02-01)
Wen, KA
;
Wuen, WS
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Huang, GW
;
Chen, LP
;
Chen, KY
There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.
Deposition of polycrystalline Si and SiGe by ultra-high vacuum chemical molecular epitaxy
(2000-07-01)
Chen, KM
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Huang, HJ
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Chang, CY
;
Chen, LP
;
Huang, GW
The polycrystalline Si1-xGex (poly-Si1-xGex) films have better properties than poly-Si for device fabrications, such as lower proceeding temperature and process thermal budget. For these reasons, the poly-Si1-xGex films have been utilized for low-temperature thin film transistor fabrications and gate electrodes of metal-oxide-semiconductor transistors. In this work, disilane and germane were used to grow poly-Si1-xGex films at low temperature (<600 degrees C) by the cold-wall type ultrahigh vacuum chemical molecular epitaxy system. The poly-Si1-xGex films were deposited on oxide and nitride surfaces. The Ge fraction x was evaluated from x-ray diffraction and Auger electron spectroscopy. It is observed that the Ge fraction increases with the increase of the GeH4 flow rate. The result is only slightly related to the substrate type. The growth rate increases with the Ge fraction at lower values and then decreases with the Ge fraction in the higher composition range. This implies that the growth mechanism of poly-Si1-xGex films is different from that of epitaxial Si1-xGex on Si. The uniformity of poly-Si1-xGex films depends on the Ge fraction, and it is improved-by the addition of germanium. The result can be explained by the lower activation energy (<0.25 eV) of poly-Si(1-x)G(x), deposition as compared to that of poly-Si (similar to 2.1 eV). From the x-ray diffraction and atomic force microscopy analyses, the crystallinity and surface roughness of films are suitable for device fabrications. (C) 2000 American Vacuum Society. [S0734-2101(00)07704-6].
Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
(1998-02-01)
Chen, LP
;
Chan, YC
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Chang, SJ
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Huang, GW
;
Chang, CY
Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
(1998-02-01)
Chen, LP
;
Chan, YC
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Chang, SJ
;
Huang, GW
;
Chang, CY
Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
Effect of coplanar probe pad design on noise figures of 0.35 mu m MOSFETs
(2000-07-20)
Su, CY
;
Chen, LP
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Chang, SJ
;
Huang, GW
;
Ho, YP
The effects of different coplanar ground-signal-ground (GSG) probe pads on the noise figure characteristics of submicron MOSFETs are presented. Devices with top-level metal as probe pads shielded by grounded bottom-level metal possess the most appropriate probe pad structure for characterising the noise performance of MOSFETs. Equivalent circuits of the probe pads are used to explain the different noise behaviours.
Effects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growth
(1997-06-01)
Tseng, HC
;
Chang, CY
;
Pan, FM
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Chen, LP
;
電子工程學系及電子研究所
Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.
Effects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growth
(1997-06-01)
Tseng, HC
;
Chang, CY
;
Pan, FM
;
Chen, LP
;
電子工程學系及電子研究所
Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.
Fabrication of thin film transistors by chemical mechanical polished polycrystalline silicon films
(1996-03-01)
Chang, CY
;
Lin, HY
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Lei, TF
;
Cheng, JY
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Chen, LP
A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP), In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm(2)/V-s, ON/OFF current ratio of 1.110(7), and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's.
High nitrogen content InGaAsN/GaAs single quantum well for 1.55 mu m applications grown by molecular beam epitaxy
(2004-02-15)
Wang, JS
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Kovsh, AR
;
Hsiao, RS
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Chen, LP
;
Chen, JF
The growth of high nitrogen content InGaAsN/GaAs single quantum well (SQW) for 1.55 mum applications on GaAs substrates using solid source molecular beam epitaxy and radio frequency plasma nitrogen source is reported. The nitrogen composition was determined using an X-ray diffractometer combined with dynamic simulation. The crystal and optical qualities of highly strained InGaAs/GaAs SQW grown at low temperature can be significantly improved by nitrogen incorporation due to reducing the lattice mismatch. Without the formation of additional nonradiative recombination in InGaAsN SQW with nitrogen composition up to 4.1% which corresponds to wavelength of 1.46 mum was achieved. The longest room-temperature PL peak wavelength obtained in this study is 1.59 mum by increasing the nitrogen composition up to 5.3%. And, the photoluminescence intensity of high nitrogen content InGaAsN SQW can be improved significantly by decreasing the growth temperature due to suppression of the phase separation of InGaAsN alloy. Our results show the potential for the fabrication of 1.55 mum InGaAsN QW lasers on GaAs substrates. (C) 2003 Elsevier B.V. All rights reserved.
Improved electrical properties of shallow p(+)-n junction using selectively grown graded Si1-xGex epitaxial structure
(2000-12-01)
Huang, HJ
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Chen, KM
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Chang, CY
;
Huang, TY
;
Chen, LP
A strained boron-doped graded Si1-xGex structure consisting of layered Si1-xGex with increasing Ge mole fractions was studied as the solid diffusion source for forming a p(+)-n junction suitable for raised source/drain metal oxide semiconductor field effect transistor (MOSFET) application. The in situ doped graded Si1-xGex structure was selectively epitaxially grown (SEG) on the active region using ultrahigh vacuum chemical molecular epitaxy (UHVCME). Improved electrical characteristics, not possible with conventional uniform SEG Si1-xGex junction, are achieved with the graded SEG Si1-xGex junction. For the conventional uniform Si1-xGex junction, while a high Ge composition is necessary for reducing the specific contact resistance and the sheet resistance, such a high Ge composition, also results in a degraded ideality factor and a leaky junction. In contrast, a near-perfect SiGe/Si interface property is demonstrated with the graded Si1-xGex structure. Optimum specific contact resistance and the sheet resistance can be obtained by the graded Si1-xGex structure without suffering degraded junction leakage and ideality factor. These results indicate that the degree of misfit dislocation and the undesirable undercut effects could be effectively reduced by using the graded structure with its lower Ge composition close to the silicon substrate, while a low sheet resistance and specific contact resistance is preserved with its higher Ge composition at the top of the layered structure. (C) 2000 The Electrochemical Society. S1099-0062(00)08-111-6. All rights reserved.
Interfacial abruptness in Si/SiGe heteroepitaxy grown by ultrahigh vacuum chemical vapor deposition
(1997-09-01)
Tsai, WC
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Chang, CY
;
Jung, TG
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Chang, TC
;
Lin, HC
High-quality Si/Si1-xGex strained-layer superlattices have been grown in the temperature range 525 degrees C-550 degrees C by ultrahigh vacuum chemical vapor deposition. We employed X-ray reflection and high-resolution double-crystal X-ray diffraction measurements to study the dimensional and compositional variations in a Si/Si1-xGex superlattice. From the X-ray reflection results, the interfacial roughness of Si layers on SiGe, and SiGe layers on Si, is 0.1nm for growth at 525 degrees C and 0.2nm for growth at 550 degrees C. A simple model for estimating the interfacial abruptness of Si/Si1-xGex heterojunctions is proposed. In this model, a transition region with a linearly graded Ge composition is assumed to exist at both Si/Si1-xGex interfaces. The Ge composition x of a Si/Si1-xGex superlattice is found to increase with the growth time at a constant gas phase composition. This phenomenon can be explained by this model, and the thickness of the transition region and the transition time can be extracted from these fitting results. The transition thicknesses are found to be about 0.3-0.7nm for growth at 525 degrees C and 1-1.5nm for growth at 550 degrees C.
Interfacial abruptness in Si/SiGe heteroepitaxy grown by ultrahigh vacuum chemical vapor deposition
(1997-09-01)
Tsai, WC
;
Chang, CY
;
Jung, TG
;
Chang, TC
;
Lin, HC
High-quality Si/Si1-xGex strained-layer superlattices have been grown in the temperature range 525 degrees C-550 degrees C by ultrahigh vacuum chemical vapor deposition. We employed X-ray reflection and high-resolution double-crystal X-ray diffraction measurements to study the dimensional and compositional variations in a Si/Si1-xGex superlattice. From the X-ray reflection results, the interfacial roughness of Si layers on SiGe, and SiGe layers on Si, is 0.1nm for growth at 525 degrees C and 0.2nm for growth at 550 degrees C. A simple model for estimating the interfacial abruptness of Si/Si1-xGex heterojunctions is proposed. In this model, a transition region with a linearly graded Ge composition is assumed to exist at both Si/Si1-xGex interfaces. The Ge composition x of a Si/Si1-xGex superlattice is found to increase with the growth time at a constant gas phase composition. This phenomenon can be explained by this model, and the thickness of the transition region and the transition time can be extracted from these fitting results. The transition thicknesses are found to be about 0.3-0.7nm for growth at 525 degrees C and 1-1.5nm for growth at 550 degrees C.
Low temperature epitaxy of Si and Si1-xGex by utrahigh vacuum-chemical molecular epitaxy
(1997-01-01)
Huang, GW
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Chen, LP
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Chou, CT
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Chen, KM
;
Tseng, HC
Pure Si2H6 and GeH4 are used to grow Si and Si1-xGex epilayers at 550 degrees C by ultrahigh vacuum-chemical molecular epitaxy. 0.1% B2H6 and 100 ppm PH3 diluted in H-2 are used as the p- and n-type dopant gases in Si/Si1-xGex epitaxy. The Ge mole fraction x and the growth rate of Si1-xGex epilayers show very strong dependence on the total source, gas flow rate ([GeH4]+[Si2H6]) and the source gas ratio ([GeH4]/[GeH4]+[Si2H6]). The results can be explained by the relationships of the source fluxes, relative incorporation efficiency at activated surface sites, and hydrogen desorption under different growth conditions. The boron concentration of Si1-xGex increases with increasing GeH4 flow rate by keeping Si2H6 and B2H6 how rates constant. It may be due to the increase of the surface sites which is caused by the increase of the hydrogen desorption rate when a higher Ge mole fraction epilayer is grown. The phosphorus concentrations of Si and Si1-xGex show different behavior with PH3 flux at higher PH3 flow rates while one increases Linearly and the other becomes saturated, respectively. These results can be explained by a model based on the different levels of the effects of phosphorus blocking of surface-activated sites between Si and Si1-xGex epilayers. This effect can also be used to explain the fact that a smaller decrease in the growth rates of Si1-xGex epilayers occurs at a higher PH3 flow rate. (C) 1997 American Institute of Physics.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Phosphorus doping of Si and Si1-xGex grown by ultrahigh vacuum chemical vapor deposition using Si2H6 and GeH4
(1996-03-11)
Chen, LP
;
Huang, GW
;
Chang, CY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
100 ppm PH3 diluted in hydrogen is used as the n-type dopant gas in Si and Si1-xGex epilayers grown by ultrahigh vacuum chemical vapor deposition (UHVCVD) using Si2H6 and GeH4. The phosphorus concentration in Si increases linearly at a small PH3 flow rate and becomes nearly saturated at higher flow rates, while the phosphorus concentration in Si1-xGex only shows a nearly linear behavior with PH3 flow rate. The growth rates of Si and Si1-xGex epilayers decrease seriously (similar to 50%) and slightly (similar to 10%) with the increase of PH3 how rate, respectively. These results con be explained by a model based on the enhancement of hydrogen desorption rate at smaller PH3 flow rates and different levels of the effects of phosphorus blocking of surface-activated sites between Si and Si1-xGex epilayers at higher PH3 flow rates. (C) 1996 American Institute of Physics.