Browsing by Author "Chen, Min-Cheng"

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3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Hsieh, Wei-Shang
;
Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications
(2012-04-01)
Chen, Min-Cheng
;
Chen, Hao-Yu
;
Lin, Chia-Yi
;
Chien, Chao-Hsin
;
Hsieh, Tsung-Fan
This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.
A Comparative Study of NBTI and RTN Amplitude Distributions in High-kappa Gate Dielectric pMOSFETs
(2012-02-01)
Chiu, J. P.
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Chung, Y. T.
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Wang, Tahui
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Chen, Min-Cheng
;
Lu, C. Y.
Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (V-t) fluctuations in high-kappa gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced Delta V-t in NBT stress and find that the average Delta V-t is significantly larger than a Delta V(t)caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced Delta V-t by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced Delta V-t indeed has a larger distribution tail than RTN due to a current-path percolation effect.
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
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Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Activating basal-plane catalytic activity of two-dimensional MoS2 monolayer with remote hydrogen plasma
(2016-12)
Cheng, Chia-Chin
;
Lu, Ang-Yu
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Tseng, Chien-Chih
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Yang, Xiulin
;
Hedhili, Mohamed Nejib
Two-dimensional layered transition metal dichalcogenide (TMD) materials such as Molybdenum disufide (MoS2) have been recognized as one of the low-cost and efficient electrocatalysts for hydrogen evolution reaction (HER). The crystal edges that account for a small percentage of the surface area, rather than the basal planes, of MoS2 monolayer have been confirmed as their active catalytic sites. As a result, extensive efforts have been developing in activating the basal planes of MoS2 for enhancing their HER activity. Here, we report a simple and efficient approach using a remote hydrogen-plasma process to creating S-vacancies on the basal plane of monolayer crystalline MoS2; this process can generate high density of S-vacancies while mainly maintaining the morphology and structure of MoS2 monolayer. The density of S-vacancies (defects) on MoS2 monolayers resulted from the remote hydrogen-plasma process can be tuned and play a critical role in HER, as evidenced in the results of our spectroscopic and electrical measurements. The H-2-plasma treated MoS2 also provides an excellent platform for systematic and fundamental study of defect-property relationships in TMDs, which provides insights for future applications including electrical, optical and magnetic devices. (C) 2016 Elsevier Ltd. All rights reserved.
Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory
(2015-02-01)
Chung, Yueh-Ting
;
Su, Po-Cheng
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Cheng, Yu-Hsuan
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Wang, Tahui
;
Chen, Min-Cheng
A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.
Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging Electrode
(2013)
Chen, Min-Cheng
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Chen, Hsiao-Chien
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Lee, Ta-Hsien
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Lin, Yu-Hsien
;
Shih, Jyun-Hung
This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (V-th shift > 60 mV/10(-16)C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.
Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal-Oxide-Semiconductor Technology
(2011-04-01)
Chen, Hou-Yu
;
Lin, Chia-Yi
;
Chen, Min-Cheng
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Huang, Chien-Chao
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Chien, Chao-Hsin
High-sensitivity polycrystalline silicon (poly-Si) nanowire field-effect transistor (NW FET) pH sensors using top-down and self-aligned fabrication approaches involving the conventional complementary metal-oxide-semiconductor (CMOS) process are reported. For the top-down NW FET, the shrinkage due to reoxidation enables the nanowire width to be scaled to 40 nm without requiring the use of extra lithography equipment, and this improves the electrical uniformity and the performance of the sensors. The surface-ionic coupling operation of this buried-channel field-effect sensor exhibits superior pH sensitivity (threshold voltage shift > 100 mV/pH) as compared to the surface-channel ion-sensitive FET (ISFET). In addition, we report a novel method for fabricating self-aligned, vertical-channel, poly-Si nanowire sensors. The resulting 65-nm self-aligned vertical-channel poly-Si device was found to be feasible for independent-gate bias control, thus enabling its possible integration in very-large-scale integration (VLSI) circuits. Both the abovementioned approaches enable the manufacture of nanowire devices on a large-scale integrated (LSI) circuit using only CMOS manufacturing processes; this provides a high sensitivity, compact and cost-efficient biosensor systems-on-a-chip application. (C) 2011 The Japan Society of Applied Physics
Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal-Oxide-Semiconductor Technology (vol 50, 04DL05, 2011)
(2018-05-01)
Chen, Hou-Yu
;
Lin, Chia-Yi
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Chen, Min-Cheng
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Huang, Chien-Chao
;
Chien, Chao-Hsin
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
;
Kao, Kuo-Hsing
;
Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
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Lin, Chia-Yi
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Li, Kai-Hsin
;
Li, Lain-Jong
;
Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
Investigation of strain-induced phase transformation in ferroelectric transistor using metal-nitride gate electrode
(2017-03-01)
Chiu, Yu-Chien
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Cheng, Chun-Hu
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Chang, Chun-Yen
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Tang, Ying-Tsan
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Chen, Min-Cheng
In this work, we report a ferroelectric memory with strainedgate engineering. The memory window of the high strain case was improved by similar to 71% at the same ferroelectric thickness. The orthorhombic phase transition (from ferroelectric to antiferroelectric transition) plays a key role in realizing negative capacitance effect at high gate electric field. Based on a reliable first principles calculation, we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. This ferroelectric strain technology shows the potential for emerging device application.
MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availability
(2016)
Li, Kai-Shin
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Wu, Bo-Wei
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Li, Lain-Jong
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Li, Ming-Yang
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Cheng, Chia-Chin Kevin
A U-shape MOS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MOS2 deposition, thin MOS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.
Nickel Silicide Formation using Pulsed Laser Annealing for nMOSFET Performance Improvement
(2011)
Chen, Hou-Yu
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Lin, Chia-Yi
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Chen, Min-Cheng
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Huang, Chien-Chao
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Chien, Chao-Hsin
The formation of a uniform, high tensile stress and low silicide/Si interfacial resistance nickel silicide in nMOSFET by introducing pulsed laser annealing (PLA) is reported. This annealing approach facilitated the phase transformation of nickel silicide to Si-rich NiSi(x) compounds using a low-thermal-budget process, improves the silicide/Si interface regularity and avoids familiar (111) NiSi(2) facet formation at a laser energy of 1.5 J cm(-2). By increasing laser energy density up to 2.3 J cm(-2), the device performance and statistics junction leakage distribution were degraded due to the increased sheet resistance of silicide layer and the destroyed silicide/Si interface morphology. When the PLA with a laser energy density of 1.5 J cm(-2) was employed for nickel silicidation on the p-type Schottky diodes, a 0.16 eV hole Schottky barrier height (SBH) increase from 0.52 to 0.68 eV was observed. In addition, the application of PLA for source/drain silicidation of nMOSFETs demonstrated an 8% enhancement in I(on) I(off) characteristic relative to that obtained through the conventional two-step rapid thermal annealing (RTA). This PLA method holds promise as a potential replacement for current nickel silicide annealing approaches toward extremely scaled-down transistors. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3601849] All rights reserved.
One-Transistor Ferroelectric Versatile Memory: Strained-Gate Engineering for Realizing Energy-Efficient Switching and Fast Negative-Capacitance Operation
(2016)
Chiu, Yu-Chien
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Cheng, Chun-Hu
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Chang, Chun-Yen
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Tang, Ying-Tsan
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Chen, Min-Cheng
In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by similar to 47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over similar to 4 decade of I-D to provide a 1 similar to 10 fA/mu m I-off and >10(8) I-on/I-off ratio, which allows for a fast 20-ns P/E switching during 10(12) cycling endurance.
Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density
(2012-04-01)
Chen, Min-Cheng
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Lin, Chia-Yi
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Chen, Bo-Yuan
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Lin, Chang-Hsien
;
Huang, Guo-Wei
The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps.
RF power FinFET transistors with a wide drain-extended fin
(2017-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chen, Hsiu-Chih
Drain-extended FinFET transistors for RF power applications have been fabricated and is presented in this paper. Power FinFETs with a wide drain extension are proposed to reduce the drain resistance. Compared with conventional drain-extended FinFETs, our proposed new devices exhibit lower on-resistances and better high-frequency performances while keeping a similar breakdown voltage. The enhancements of the on-resistance and peak cutoff frequency are 16 and 56%, respectively, under an optimal drain-extension layout. These experimental results suggest that FinFET transistors with a wide drain extension could be used for RF power applications, increasing the possibility of integrating RF power parts into future FinFET system-on-a-chip technologies. (C) 2017 The Japan Society of Applied Physics
SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory
(2016-06)
Chung, Yueh-Ting
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Su, Po-Cheng
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Lin, Wen-Jie
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Chen, Min-Cheng
;
Wang, Tahui
Characterization and modeling of SET/RESET cycling-induced SET-disturb failure time degradation in a tungsten oxide resistive random access memory are performed. We find that write-disturb failure time in a high-resistance state (HRS) cell abruptly degrades by the orders of magnitude after certain SET/RESET cycles. To investigate this new degradation mode, we perform the constant voltage stress in high-resistance state (HRS) to characterize the trap generation in a switching dielectric by measuring a stress-induced leakage current and a low-frequency noise. The constant voltage stress is to emulate high-field stress and, thus, trap creation in SET/RESET cycling. We find that a low-field current in HRS by trap-assisted tunneling in a rupture region gradually increases in both the constant voltage stress and the SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A 3-D Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both the stress-generated traps and the SET-disturb-induced oxygen vacancies. The model can well explain the observed abrupt and the drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps.
Silicide Barrier Engineering Induced Random Telegraph Noise in 1Xnm CMOS Contacts
(2011)
Chen, Min-Cheng
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Lin, Chia-Yi
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Chen, Bo-Yuan
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Lin, Chang-Hsien
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Huang, Guo-Wei
For the first time, new random telegraph noise behaviors are reported for silicide band gap engineering in advanced nano CMOS technology. Noise current pulses of up to 40% magnitude are observed when Schottky barrier is reduced to 0.2eV. The large contact resistance instability is attributed to barrier modification at Schottky contact interface by positive charge trapping. The prevalence and magnitude of the noise are dependent on the contact size, trap density, trap energy and the silicide Schottky barrier height. In this work, we report a fast monitor methodology to identify the silicide process induced traps in small silicide contacts for 1Xnm CMOS technology.
Statistical Characterization and Modeling of the Temporal Evolutions of Delta V-t Distribution in NBTI Recovery in Nanometer MOSFETs
(2013-03-01)
Chiu, Jung-Piao
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Liu, Yu-Heng
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Hsieh, Hung-Da
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Li, Chi-Wei
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Chen, Min-Cheng
NBTI trapped charge characteristics and recovery mechanisms are examined by a statistical study of individual trapped charge emissions in nanoscale HfSiON/metal gate pMOSFETs. We measure individual trapped charge emission times in NBTI recovery in a large number of devices. The characteristic time distributions of the first three emitted holes are obtained. The distributions can be well modeled by using a thermally-assisted tunnel (ThAT) detrapping model. NBTI trapped charge energy and spatial distributions and its activation energy distribution in the ThAT model are discussed and extracted. Based on the ThAT model and measured result of single-charge induced V-t shifts, we develop a statistical NBTI recovery Delta V-t evolution model. Our model can well reproduce the temporal evolutions of a Delta V-t distribution in a number of NBTI stressed nanometer MOSFETs in relaxation.