SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory

Abstract

Characterization and modeling of SET/RESET cycling-induced SET-disturb failure time degradation in a tungsten oxide resistive random access memory are performed. We find that write-disturb failure time in a high-resistance state (HRS) cell abruptly degrades by the orders of magnitude after certain SET/RESET cycles. To investigate this new degradation mode, we perform the constant voltage stress in high-resistance state (HRS) to characterize the trap generation in a switching dielectric by measuring a stress-induced leakage current and a low-frequency noise. The constant voltage stress is to emulate high-field stress and, thus, trap creation in SET/RESET cycling. We find that a low-field current in HRS by trap-assisted tunneling in a rupture region gradually increases in both the constant voltage stress and the SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A 3-D Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both the stress-generated traps and the SET-disturb-induced oxygen vacancies. The model can well explain the observed abrupt and the drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps.