Browsing by Author "Chen, Po-Hung"

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A 13.56 MHz Pulse-Width Modulation Active Rectifier for Implantable Medical Devices
(2017-01-01)
Yang, Fu-Bin
;
Hsieh, Sheng-Kai
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Chen, Po-Hung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 13.56 MHz regulated dual-output active rectifier is proposed for implantable medical devices (IMDs). By adopting the pulse-width modulation (PWM) to control the conduction time of the rectifying switches, the proposed active rectifier is able to realize the rectification and regulation of dual-output voltages without adding DC-DC converters. The proposed automatic digital offset compensation (ADOC) can automatically compensate both turn-on and turn-off delay to maximize the conversion power and minimize the reverse current. Dual-output voltages 1.8 V and 3.3 V are generated to supply the internal circuit in IMDs. The simulated maximum power conversion efficiency (PCE) is 78.5%, and the input operating voltage ranges from 3.6 V to 5 V. Comparing to the conventional constant offset calibration, the efficiency improvement of 8% is obtained.
A 13.56MHz Power-Efficient Active Rectifier with Digital Offset Compensation for Implantable Medical Devices
(2016)
Fuh, Jonathan
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Hsieh, Sheng-Kai
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Yang, Fu-Bin
;
Chen, Po-Hung
;
電子工程學系及電子研究所
In this paper, a 13.56 MHz power-efficient CMOS active rectifier is proposed for implantable medical devices. The digital offset compensation technique automatically compensates the turn-off delay to minimize the reverse leakage current to improve the conversion efficiency. The simulation results show that the proposed rectifier achieves 92.9% PCE with wide input voltage range. The input operating voltage ranges from 1.5V to 4.5V and the efficiency improvement of 6.5% is also obtained.
A 13.56MHz Wireless Power Transfer System with Dual-Output Regulated Active Rectifier for Implantable Medical Devices
(2018-01-01)
Yang, Fu-Bin
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Fuh, Jonathan
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Chen, Po-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 13.56 MHz wireless power transfer system with dual-output regulated active rectifier is developed for implantable medical devices. The rectifier employs pulse-skip modulation (PSM) to regulate two output voltages without using power consuming low dropout regulators (LDOs). The proposed automatic digital offset compensation adjusts both turn-on timing and turn-off timing to compensate the turn-on and turn-off delays of the comparator. The simulation results show that the proposed active rectifier achieves 94% efficiency. The entire wireless power transmission system including power amplifier, resonant tanks, and rectifier, has 67.2% maximum power conversion efficiency (PCE). Compared to the conventional approach with ideal LDOs, 19.2% efficiency improvement is obtained.
A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting
(2016-02)
Chen, Po-Hung
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Wu, Chung-Shiang
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Lin, Kai-Chun
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交大名義發表
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National Chiao Tung University
This paper presents a tri-mode digital buck converter in 0.18-mu m CMOS technology for photovoltaic energy harvesting. The on-chip gate-boosted digital pulsewidth modulation (DPWM) improves the conversion efficiency at heavy load conditions. Pulse-frequency modulation (PFM) along with digital self-tracking zero current detection is proposed to avoid reverse current at light load. The asynchronous mode (AM) operation further reduces the controller loss and improves the conversion efficiency at ultra-light load conditions. By applying DPWM, PFM, and AM at different load conditions, the proposed converter provides a maximum conversion efficiency of 92% with output power ranging from 50 nW to 10 mW. In addition, the proposed buck converter achieves more than 70% efficiency from 400 nW to 10 mW output power.
A 50nW-to-10mW Output Power Tri-Mode Digital Buck Converter with Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting
(2015-01-01)
Chen, Po-Hung
;
Wu, Chung-Shiang
;
Lin, Kai-Chun
;
交大名義發表
;
National Chiao Tung University
A 69.3% Efficiency, 6.78-MHz Wireless Power Delivery System with 0X/1X Regulating Rectifier and Reconfigurable Power Amplifier
(2019-01-01)
Fuh, Jonathan
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Yang, Fu-Bin
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Chen, Po-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a 6.78-MHz highefficiency wireless power transfer system with a reconfigurable class-D power amplifier and a 0X/1X regulating rectifier. The proposed reconfigurable power amplifier delivers 0.25X/1X output power by adjusting the power-stage configuration to improve system efficiency. To enhance the receiver efficiency, the proposed 0X/1X regulating rectifier with adaptive offset compensation achieves both voltage rectification and voltage regulation in a single conversion stage. The measurement results demonstrate a 90.1% peak receiver efficiency and a 69.3% peak system efficiency. The system provides the load circuit with 5-V regulated output and 250-mW maximum output power.
A Fully Integrated Light-Powering System with Integrated CMOS Photovoltaic Cell for Batteryless IoT Devices
(2019-01-01)
Chen, Po-Han
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Huang, Chao-Yi
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Cheng, Hao-Chung
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Chen, Po-Hung
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電子工程學系及電子研究所
This paper presents a fully integrated CMOS lightpowering system, integrating CMOS photovoltaic cell and energy harvesting interface, for batteryless internet of things (IoT). The CMOS photovoltaic cell employs deep N-well (DNW) based structure to improve the light-electric conversion efficiency. The energy harvesting interface utilizes a fully integrated two-stage switched-capacitor dc-dc converter to provide an appropriate output voltage for load circuits. It provides 1 V and 0.9 - 1.1 V output under light load and heavy load, respectively. The chip is designed and fabricated by 180-nm CMOS process, without using any off-chip components, except a storage capacitor for testing. The experimental results demonstrate that the proposed 1mm x 2mm fully integrated light-powering system can periodically provide 0.9 V to 1.1 V output voltage to power 1-mA loading circuit. The proposed interface achieves 70 percent peak-efficiency at 1 mu A and higher than 60 percent efficiency over 0.5 mu A to 2 mu A loading currents.
A Fully Integrated Step-Down Switched-Capacitor DC-DC Converter With Dual Output Regulation Mechanisms
(2020-09-01)
Chen, Po-Han
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Cheng, Hao-Chung
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Chen, Po-Hung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter proposes a fully integrated step-down switched-capacitor (SC) DC-DC converter using 0.18-mu m CMOS technology for system-on-chip applications. The proposed stepdown switched-capacitor DC-DC converter used two control mechanisms: the switch array modulation technique to regulate the output voltage and the voltage ripple modulation technique to adjust the output voltage ripple of the converter as the loading current varied. As a result, the proposed converter could generate a regulated output voltage with low voltage ripple. The converter core performed at conversion ratios of 1/3 and 1/2 under an input voltage of 1.8 V. The measurement results on 180-nm technology showed that the proposed fully integrated step-down switched-capacitor DC-DC converter could achieve a peak power conversion efficiency of 74.1% and maintain power conversion efficiency at levels over 70% within loading ranges between 1.4 and 5 mA. The output voltage ripple was controlled at levels under 63.4 mV within a loading current ranging between 0.1 and 5 mA.
A Fully-Integrated Charge Pump for Self-Powered Implantable Retinal Prostheses
(2016)
Wong, Oi-Ying
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Chen, Po-Hung
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Wu, Chung-Yu
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
This paper presents a compact fully-integrated charge pump based voltage doubler for self-powered implantable retinal prostheses. The target input voltage is 0.55 V to meet the output voltage of on-chip photovoltaic cells, and the target output is around 1 V to provide sufficient current for neuron stimulation. Several techniques are adopted in the proposed design, including gate-boosting circuits to enhance current driving capability, a time-interleaving technique to reduce the size of the output capacitor, and a non-overlapping clock generator to suppress the shoot-through current. The proposed charge pump was implemented in 0.18 mu m CMOS process with core chip area of 700 mu m x 280 mu m. The measurement results demonstrate that the proposed charge pump is capable of providing around 1 V output from an input voltage of 0.55 V with 500 mu A loading current. The peak power efficiency is 73.4 % and the total area is 700 mu m x 280 mu m.
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
(2016-04)
Zimmer, Brian
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Lee, Yunsup
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Puggelli, Alberto
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Kwak, Jaehwa
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Jevtic, Ruzica
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
(2016-04-01)
Zimmer, Brian
;
Lee, Yunsup
;
Puggelli, Alberto
;
Kwak, Jaehwa
;
Jevtic, Ruzica
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.
A Single-Inductor Dual-Input Dual-Output (SIDIDO) Power Management with Sequential Pulse-Skip Modulation for Battery/PV Hybrid Systems
(2016-01-01)
Lee, Hui-Hsuan
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Chen, Po-Hung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a single-inductor dual-input dual output (SIDIDO) power converter with sequential pulse-skip modulation (SPSM) is proposed for IoT applications. It manages power from a 1.4-V zinc-air battery and a 0.55-V to 0.7-V photovoltaic (PV) module to prolong the battery life. The proposed converter employs buck-boost mode and buck mode for PV module and the battery, respectively, to produce two different output voltages. The input sources are automatically selected by mode detection circuit which monitors both PV voltage and the output voltage to minimize the battery usage. The proposed SPSM along with a constant voltage maximum power point tracking (MPPT) method controls output voltages with low cross regulation while extracting the maximum power from a PV module. The measurement results demonstrate a peak efficiency of 89 % with an available input voltage of 0.55 V to 1.4 V.
A Single-Inductor Dual-Ouput (SIDO) DC-DC Converter for Implantable Medical Devices in 180nm Standard CMOS Process
(2018-01-01)
Liao, Pei-Chun
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Chen, Yi-Lun
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Chen, Po-Hung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a single-inductor dual-output (SIDO) buck converter is developed for implantable medical devices. The stacked power stage with startup circuit is designed to avoid over-stress issue in 180nm CMOS process for 3.4 V to 5 V battery input. The converter provides two regulated outputs for the charge pump (V-OUT1 = 3 V) and the digital circuits (V-OUT2 = 2 V) with low cross regulation with pulse-skip modulation. An adaptive on-time (AOT) circuit adjusts on time dynamically based on the input voltage (V-IN) to obtain high conversion efficiency and low output voltage ripple under different V-IN. The measurement results demonstrates that the proposed converter achieves peak efficiency of 93.6% with an available input voltage of 3.4 V to 5 V.
A Single-Inductor Triple-Input-Triple-Output (SITITO) Energy Harvesting Interface with Cycle-by-Cycle Source Tracking and Adaptive Peak-Inductor-Current Control
(2017-01-01)
Liu, Chi-Wei
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Chung, Ming-Jie
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Lee, Hui-Hsuan
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Liao, Pei-Chun
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Chen, Po-Hung
In this paper, a single-inductor triple-input-triple-output (SITITO) buck-boost converter with cycle-by-cycle source tracking (CCST) is developed for multi-source energy harvesting. The proposed CCST is capable of harvesting power from the PV and TEG simultaneously, and automatically selects the appropriate source according to the maximum power point (MPP) of the transducers in each switching cycle. The converter provides two regulated outputs for the analog (V-OUT1 = 1.2 V) and the digital (V-OUT2 = 0.4-0.6 V) circuits, while storing the excess energy in a storage capacitor (C-OUT3). An adaptive on-time (AOT) circuit with an adaptive peak-inductor-current (APIC) control is developed for dynamically adjusting the on-time based on the input voltage (V-IN) to obtain high conversion efficiency under different V-IN. The proposed converter achieves a peak efficiency of 84.4% with an available input voltage of 0.05 V to 0.8 V. Compared to the conventional constant peak-inductor-current (CPIC) control, the proposed APIC improves 11 % efficiency at low V-IN.
A Single-Inductor Triple-Source Quad-Mode Energy-Harvesting Interface With Automatic Source Selection and Reversely Polarized Energy Recycling
(2019-10-01)
Chen, Po-Hung
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Cheng, Hao-Chung
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Lo, Chih-Lun
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a single-inductor triple-source quad-mode (SITSQM) energy-harvesting interface in a 0.18-mu m CMOS process. The proposed reversely polarized energy recycling (RPER) technique improves not only the conversion efficiency at low input voltage but also the system's output power range. The interface employs the buck-boost topology to convert energy from photovoltaic (PV) cells and a thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter features four different operating modes, namely, harvesting, recycling, storing, and backup. The operating mode is automatically selected according to the input and load conditions using the automatic source selection mechanism. The experimental results demonstrate 25.3% efficiency improvement and 10x output power range extension from the proposed RPER technique. The proposed SITSQM converter automatically manages three harvesting sources with 82.1% peak conversion efficiency.
A Tri-Mode Fully-Integrated Capacitive Voltage Multiplier for Photovoltaic Energy Harvesting
(2017-01-01)
Cheng, Hao-Chung
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Lin, Min-Yen
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Chen, Po-Hung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a tri-mode fully-integrated capacitive voltage multiplier is proposed. The system provides power conversion efficiency over 60% within the loading current ranges from 60 mu A to 160 mu A. The input voltage (V-IN) ranges from 0.45-0.7V to meet the output of photovoltaic cells, and the output voltage (V-OUT) is set as 1.2V. The proposed tri-mode operation combines doubler mode, tripler mode and boosting mode to cover wide input voltage range. The doubler mode is implemented by utilizing a single-stage charge pump (CP) circuit while the tripler mode is realized by connecting two CP stages in series. The boosting mode enlarges the gate swing of the second CP power stage to further reduce the conduction loss of the power transistors, which allows the system to operate at 0.45-V V-IN. The regulation controller consists of the coarse/fine modulators and mode selection circuit. By applying the proposed regulation and reconfigurable techniques, the system is able to switch operating mode automatically as input voltage varies. To achieve low power and low voltage operation, all regulation systems are built by digital circuits. From simulation results, the peak power conversion efficiency of 89% is achieved at 100-mu A output current.
An 82.1%-Power-Efficiency Single-Inductor Triple-Source Quad-Mode Energy Harvesting Interface with Automatic Source Selection and Reversely Polarized Energy Recycling
(2018-01-01)
Lo, Chih-Lun
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Cheng, Hao-Chung
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Liao, Pei-Chun
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Chen, Yi-Lun
;
Chen, Po-Hung
In this paper, a single-inductor triple-source quad mode energy harvesting interface with automatic source selection is developed for multi-source energy harvesting. The interface employs buck-boost topology to convert the energy from photovoltaic (PV) cells and thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter has four operating modes: harvesting mode (BM), recycling, mode (RM), storage mode (SM), and backup mode (BM). The operating mode is selected automatically according to the input and load conditions to appropriately transfer the energy. The proposed reversely polarized energy recycling (RPER) technique extends the available output power range by 10x with 25.3% efficiency improvement at low input voltage. The measurement results demonstrates the proposed interface achieves the peak efficiency of 82.1%.
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS
(2019-05-01)
Liu, Chi-Wei
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Chen, Yi-Lun
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Liao, Pei-Chun
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Lin, Shiau-Pin
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Wang, Ting-Wei
This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.
An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting
(2015-02-01)
Chen, Po-Hung
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Fan, Philex Ming-Yan
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a 100 mV input, 500 mV output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 mu m CMOS technology for thermoelectric energy harvesting. The proposed AGB technique and near-threshold voltage (near-V-TH) energy redistribution control (ERC) ensure high conversion efficiency over a wide range of load currents. The proposed method automatically reduces conduction and switching losses of power MOSFETs without the need for auxiliary power converters or additional off-chip inductors. The AGB technique reduces conduction and switching losses under heavy-load and light-load conditions, respectively. The experimental results show that the efficiency of the proposed converter is enhanced by 25.5% and 18% at output load currents of 1500 mu A and 50 mu A, respectively. The proposed step-up dc-dc converter achieves the lowest output voltage and provides the highest conversion efficiency of 83.4% to date in standard CMOS process for thermoelectric energy harvesting.
An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications
(2015)
Wu, Chung-Shiang
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Lin, Kai-Chun
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Kuo, Yi-Ping
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Chen, Po-Hung
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Chu, Yuan-Hua
A 1V similar to 1.2V battery input, 0.4V similar to 0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switchedcapacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30 mu W to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/ 130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.