Browsing by Author "Chen, TY"

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A weight-assessing method with habitual domains
(1998-10-16)
Tzeng, GH
;
Chen, TY
;
Wang, JC
;
管理學院
;
College of Management
Weights of criteria are the important factors in decision-making. However, from a behavioral perspective, traditional weighting methods account for too few factors to deal with decisions properly. Based on the behavior mechanism and the theory of habitual domains, this study is undertaken to develop a new weight-assessing model that treats decisionmaking as a dynamically adjusting process proceeding from the ideal to actual states. The new model is built upon the dynamic analysis for the connectivities between criteria instead of the static analysis of traditional models. Finally, we have studied Taipei City motorcycle users, mode-choice behavior through questionnaire in order to show the applicability of the new model. From the empirical results, it is found that our weight-assessing method has significant application potential in practice. (C) 1998 Elsevier Science B.V. All rights reserved.
Activation of p-type GaN in a pure oxygen ambient
(2001-05-15)
Wen, TC
;
Lee, SC
;
Lee, WI
;
Chen, TY
;
Chan, SH
In this study, we activated p-type GaN in a pure oxygen ambient by rapid thermal annealing. The sheet resistance of p-type GaN was greatly reduced from > 10(7) Omega/square to 7.06 x 10(4) Omega/square after annealing in oxygen ambient at 500 degreesC, The photoluminescence intensity of blue emission increased by one order of magnitude compared to the as-grown sample. Moreover, the sheet resistance of p-type GaN annealed in pure oxygen ambient is lower than that of p-type GaN annealed in nitrogen ambient. The carrier concentrations of the samples annealed in oxygen ambient are higher than those annealed in nitrogen ambient. The better activation of p-type GaN in oxygen ambient is due to the higher activity of oxygen than that of nitrogen. Oxygen would remove hydrogen that passivates Ma atoms by forming H2O at a lower temperature.
An examination of the wind-driven effect on the drift of precipitation particles using the Chung-Li VHF radar
(1997-05-01)
Chu, YH
;
Chen, TY
;
Lin, TH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
One of the essential assumptions made in estimating the terminal velocity and the drop-size distribution of hydrometeor from the precipitation Doppler spectrum observed by VHF/UHF radar (or wind profiler) is that all of the precipitation particles are moving together at the same velocity as the ambient wind. However, this may not be the case. In this paper, taking advantage of the capability of simultaneously measuring the motions of precipitation particles and the clear-air turbulence with a VHF radar, we develop a method to examine the wind-driven effect on the drift of precipitation particles using the Chung-Li VHF radar. By appropriately setting the radar parameters and steering the radar beams, experimental results show that the drift velocity of the precipitation particles in response to the drag force exerted by the background atmosphere is not the same as the ambient wind velocity, approximately 83% of the latter in this case. This feature indicates that the precipitation particles are not moving with the background wind, causing inaccurate estimations of the terminal velocity and the drop-size distribution of hydrometeor if this effect is not taken into account.
An examination of the wind-driven effect on the drift of precipitation particles using the Chung-Li VHF radar
(1997-05-01)
Chu, YH
;
Chen, TY
;
Lin, TH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
One of the essential assumptions made in estimating the terminal velocity and the drop-size distribution of hydrometeor from the precipitation Doppler spectrum observed by VHF/UHF radar (or wind profiler) is that all of the precipitation particles are moving together at the same velocity as the ambient wind. However, this may not be the case. In this paper, taking advantage of the capability of simultaneously measuring the motions of precipitation particles and the clear-air turbulence with a VHF radar, we develop a method to examine the wind-driven effect on the drift of precipitation particles using the Chung-Li VHF radar. By appropriately setting the radar parameters and steering the radar beams, experimental results show that the drift velocity of the precipitation particles in response to the drag force exerted by the background atmosphere is not the same as the ambient wind velocity, approximately 83% of the latter in this case. This feature indicates that the precipitation particles are not moving with the background wind, causing inaccurate estimations of the terminal velocity and the drop-size distribution of hydrometeor if this effect is not taken into account.
Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process
(2003-08-01)
Chen, TY
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The layout dependence on ESD robustness of P40S and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate. edge at drain And source regions, the. spacing from,the drain diffusion to the guardring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in, the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between. ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the, energy band diagrams.
Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
(2001)
Ker, MD
;
Lo, WY
;
Chen, TY
;
Tang, H
;
Chen, SS
An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mum shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.
Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
(2002-09-01)
Ker, MD
;
Chen, TY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mum/mum) in a 0.35-mum silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications
(2000)
Ker, MD
;
Chen, TY
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the HEM (MM) ESD level of up to 6kV (400V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond pad capacitance) for high-frequency applications.
Design on ESD protection circuit with very low and constant input capacitance
(2001)
Chen, TY
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
(2000-08-01)
Ker, MD
;
Chen, TY
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond-pad capacitance) for high-frequency applications.
ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
(2001)
Chen, TY
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-mum and 0.35-mum CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HEM (Human-Body-Model) ESD level of NMOS with a W/L of 300 mum/0.3 mum can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the subquarter-micron CMOS process.
Identification of general fuzzy measures by genetic algorithms based on partial information
(2000-08-01)
Chen, TY
;
Wang, JC
;
Tzeng, GH
;
管理學院
;
College of Management
This study develops an identification procedure for general fuzzy measures using genetic algorithms, In view of the difficulty in data collection in practice, the amount of input data is simplified through a sampling procedure concerning attribute subsets, and the corresponding detail design is adapted to the partial information acquired by the procedure. A specially designed genetic algorithm is proposed for better identification, including the development of the initialization procedure, fitness function, and three genetic operations. To show the applicability of the proposed method, this study simulates a set of experimental data that are representative of several typical classes. The experimental analysis indicates that using genetic algorithms to determine general fuzzy measures can obtain satisfactory results under the framework of partial information.
Identification of V23RalA-Ser(194) as a critical mediator for aurora-A-induced cellular motility and transformation by small pool expression screening
(2005-03-11)
Wu, JC
;
Chen, TY
;
Yu, CTR
;
Tsai, SJ
;
Hsu, JM
Human Aurora kinases have three gene family members: Aurora-A, Aurora-B, and Aurora-C. It is not yet established what the specificity of these kinases are and what signals relayed by their reactions. Therefore, we employed small pool expression screening to search for downstream substrates of Aurora-A. Interestingly, all of the identified Aurora-A substrates were resistant to serve as substrates for Aurora-B or Aurora-C, suggesting that these Aurora family members may have distinct substrate specificity for propagation of diverse signaling pathways, even though they share a conserved catalytic kinase domain. Of the candidate substrates, Aurora-A could increase the functional activity of RalA. Mutational analysis revealed that RalA-Ser(194) was the phosphorylation site for Aurora-A. Ectopic expression of V23RalA-WT could enhance collagen I-induced cell migration and anchorage-independent growth in Madin-Darby canine kidney (MDCK) Aurora-A stable cell lines. In contrast, overexpression of V23RalA-S194A in MDCK Aurora-Astable cell lines abolished the intrinsic migration and transformation abilities of Aurora-A. To our knowledge, this is the first systematic search for the downstream substrates of Aurora-A kinase. Moreover, these results support the notion that Aurora-A may act in concert with V23RalA through protein phosphorylation on Ser(194) to promote collagen I-induced cell motility and anchorage-independent growth in MDCK epithelial cells.
Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology
(2001)
Ker, MD
;
Hong, KK
;
Chen, TY
;
Tang, H
;
Huang, SC
Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-mum partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
(2002-01-01)
Ker, MD
;
Chen, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for high-frequency applications. The device dimension (W/L) of ESD protection device connected to the I/O pad can be reduced to only 50 mum/0.5 mum in a 0.35-mum silicided CMOS process, but it can sustain HBM (MM) ESD level up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to0.4 pF for high-frequency applications. This input capacitance can be further reduced if the ESD protection devices are designed with smaller device dimensions. Moreover, by using the optimized layout design to draw the layout of ESD protection NMOS and PMOS devices, the voltage-dependent variation on input capacitance of this analog ESD protection circuit can be kept below 1% under an input voltage swing of 1 V. With such almost constant input capacitance, the nonlinear distortion causing by on-chip ESD protection circuit can be minimized for high-precision applications. (C) 2002 Elsevier Science B.V. All rights reserved.
Low-etch-pit-density GaN substrates by regrowth on free-standing GaN films
(2002-05-20)
Tsai, CC
;
Chang, CS
;
Chen, TY
;
光電工程學系
;
Department of Photonics
In this study, GaN substrates with low-density etch pits were obtained by regrowth on free-standing GaN films (two steps) by hydride vapor-phase epitaxy (HVPE). The etch-pit density was lower than 4x10(4) cm(-2) by atomic-force microscopy. The density is significantly lower than that of the HVPE-grown (one-step) GaN films (HVPE GaN), using sapphire as a substrate. The optical and electrical properties of the two-step HVPE-grown GaN substrates are superior to those of HVPE GaN. Temperature-dependent photoluminescence measurements reveal that thermal quenching behavior of the 2.9 eV band is possibly attributed to a shallow acceptor level at about 118+/-5 meV above the valence band. (C) 2002 American Institute of Physics.
Magnetic switching and reversal process in a tip ring structure
(2004-06-01)
Liou, Y
;
Chen, DC
;
Yu, C
;
Chen, JS
;
Lee, SF
Patterned Permalloy submicron-size structures have been fabricated by e-beam lithography in the shape of a ring with a tip. A tip was intentionally added into the ring as a geometrical defect to interrupt the continuity of the magnetization, which aligns along the ring, in order to pin the domain wall. Magnetic switching and reversal process have been measured by the magnetoresistance measurement. The switching field about 260 Oe was obtained. At the remanent state, there was a 0.21% difference in the magnetoresistance between the angles of 90degrees and 0degrees that was equivalent to the domain wall magnetoresistance. By applying an external field, the domain wall moved along the ring under a lower field (100 Oe), which is smaller than the switching field. A drop (0.24%) in the resistance between the angle of 70degrees-120degrees has been observed that means the domain wall was moving into the voltage measuring region during the rotation. (C) 2004 American Institute of Physics.
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
(1998-06-01)
Ker, MD
;
Wu, CY
;
Huang, CC
;
Chen, TY
;
電子工程學系及電子研究所
A new multiple-cell square-type layout design is proposed to realize the large-dimension output transistors for submicron low-voltage CMOS ICs. By using this layout design, the layout area of CMOS output buffers can be effectively reduced 30-40% with respect to the traditional finger-type layout. The drain-to-bulk parasitic capacitance of the output transistors is also reduced 40% by this square-type layout. Experimental results in a 0.6 mu m CMOS process have shown that the maximum driving (sinking) capability per unit layout area of a CMOS output buffer realized by the proposed multiple-cell square-type layout is improved 54% (34%) more than that by the traditional finger-type layout. The human-body-model (machine-model) ESD robustness per unit layout area of the CMOS output buffer realized by the proposed multiple-cell square-type layout is increased 25.2% (17.3%) as comparing to that by the traditional finger-type layout. (C) 1998 Published by Elsevier Science Ltd. All rights reserved.
Neural-network-identification-based adaptive control of wing rock motions
(2005-01-01)
Hsu, CF
;
Lin, CM
;
Chen, TY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
The proposed control system comprises a computation controller and a tracking controller. The computation controller containing a recurrent neural network identifier is the principal controller, and the tracking controller is designed to achieve L-2 tracking performance with a desired attenuation level. To investigate the effectiveness of the proposed control system the design methodology is used to control a wing rock motion, manifested by a limit-cycle oscillation predominantly for an aircraft operating at subsonic speeds and high angles of attack. Simulation results demonstrate that the proposed control system can achieve favourable tracking performance for the wing rock motion.
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
(1999-03-01)
Ker, MD
;
Chen, TY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout. (C) 1999 Elsevier Science Ltd. All rights reserved.