Browsing by Author "Chen, Wei-Chen"

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A Novel Double-gated Nanowire TFT and Investigation of Its Size Dependency
(2009)
Chen, Wei-Chen
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Lin, Chuan-Ding
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Lin, Horng-Chih
;
Huang, Tiao-Yuan
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電子工程學系及電子研究所
A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated Configuration, the function of threshold voltage modulation is investigated.
A Reliable Brain Computer Interface Implemented On FPGA For Mobile Dialing System
(2015)
Feng, Chih-Wei
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Chang, Jui-Chung
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Chen, Wei-Chen
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Fang, Wai-Chi
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電子工程學系及電子研究所
This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
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Lin, Horng-Chih
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Lin, Zer-Ming
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Hsu, Chin-Tsai
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Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
;
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Hsu, Chin-Tsai
;
Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
An EEG Analog Front-End Design with Wireless Communication Module for a Portable EEG Monitoring System
(2015)
Chen, Wei-Chen
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Chen, Yi-Chung
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Chou, Chia-Ching
;
Fang, Wai-Chi
;
電機學院
In this paper, a wireless electroencephalography (EEG) acquisition analog front-end (AFE) circuit design is presented. The wireless EEG acquisition system includes an analog front-end readout chipset (AFERC) with extendable channel, a low-power MSP430 microcontroller from Texas Instruments and a commercial Bluetooth 2.0 module (BTM). The front-end readout chipset not only applies the ability of noise attenuation but also modulates the EEG signal into appropriate amplitude. It has individual 10-bit successive approximation register analog-to-digital converter (SAR-ADC) for each EEG channel, and it transmits the EEG signals which have been serially converted to digital format to MSP430. MSP430 is responsible for rearranging the converted digital bits and controlling the BTM with built-in Universal Asynchronous Receiver/Transmitter (UART) interface. The AFERC maximumly reaches to 64 channels, and single channel consumes 80.268 uW. Total power consumption of AFERC is 2.6 mW at with 32 channels, and its Common-Mode-Reject-Ratio (CMRR) is 75 dB.
Bayesian Tree Search for Beamforming Training in Millimeter Wave Wireless Communication Systems
(2018-01-01)
Chen, Wei-Chen
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Chiu, Hsiao-Ting
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Gau, Rung-Hung
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電信工程研究所
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Institute of Communications Engineering
In this paper, we propose novel algorithms of beamforming training for millimeter wave wireless communication systems. Instead of searching the whole codebook organized as a binary tree, we propose using Bayesian tree search algorithms to reduce the average delay of beamforming training. In addition, we design algorithms that derive an optimal threshold for the proposed opportunistic one-threshold tree search algorithm and an optimal pair of thresholds for the proposed opportunistic two-threshold tree search algorithm. Furthermore, we propose using quantization to efficiently calculate the likelihood ratio in the proposed opportunistic tree search algorithms. Our simulation results show that the proposed algorithms could significantly reduce the average delay of beamforming training.
Effects of independent double-gated configuration on polycrystalline-Si nonvolatile memory devices
(2009-09-28)
Chen, Wei-Chen
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Lin, Horng-Chih
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Chang, Yu-Chia
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Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A polycrystalline-Si thin-film transistor configured with independent double-gated structure and ultrathin channel film is proposed for use as a Si-oxide-nitride-oxide-Si memory device. Taking advantage of additional control gate bias offered by the independent double-gated scheme in addition to the driving gate, this work demonstrated that the reading window and programming efficiency can be improved by applying a proper control gate bias. It is also found that the relationship between programming/erasing speed and control gate bias is strongly related to channel film thickness. Our results indicate that the independent double-gated device possesses promising potential for future nonvolatile memory applications. (C) 2009 American Institute of Physics. [doi: 10.1063/1.3238362]
Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors
(2009-09-01)
Liu, Wen
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Liou, Juin J.
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Chung, Andy
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Jeong, Yoon-Ha
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Chen, Wei-Chen
Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and ON-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.
Impact of V-pass Interference on Charge-Trapping NAND Flash Memory Devices
(2015-06-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chang, Kuo-Pin
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Tsui, Bing-Yue
The impact of adjacent word-line\'s pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.
Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices
(2011-07-01)
Luo, Cheng-Wei
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Lin, Horng-Chih
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Lee, Ko-Hui
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Chen, Wei-Chen
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Hsu, Hsing-Hui
Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.
In Situ Doped Source/Drain for Performance Enhancement of Double-Gated Poly-Si Nanowire Transistors
(2010-07-01)
Chen, Wei-Chen
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Lin, Horng-Chih
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Chang, Yu-Chia
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Lin, Chuan-Ding
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Huang, Tiao-Yuan
A poly-Si nanowire (NW) thin-film transistor configured with the double-gated scheme was fabricated and characterized. The fabrication process features the clever use of selective plasma etching to form a rectangular NW underneath a hard mask. In this paper, we show that replacing the original ion-implanted poly-Si with in situ doped poly-Si for the source/drain significantly enhances the device performance, including steeper subthreshold swing (SS), larger on/off current ratio, and reduced series resistance. In particular, the SS is improved to a record-breaking low value of 73 mV/dec, which, to the best of our knowledge, is the most ideal ever reported for a poly-Si based device. The new NW transistors with such excellent switching properties are highly promising for reducing power consumption and operational voltage in practical circuit applications.
Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel
(2010-02-15)
Lin, Zer-Ming
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Lin, Horng-Chih
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Chen, Wei-Chen
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
In this letter, characteristics of independently-controllable double-gated polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with ultrathin channel are characterized and analyzed experimentally and theoretically. As compared with the single-gated mode where only one of the gates is used for driving the device, 1.3-2.1 fold increase in drive current is achieved under double-gated mode as the two gates are biased simultaneously for driving the device. A remarkable lowering of barrier height 7-12 meV in the latter case due to the coupling of the two gate biases is identified as the major origin for such performance enhancement.
Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations
(2011-08-01)
Chen, Wei-Chen
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Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, we investigate the merits of an independent double-gated configuration for nonvolatile memory operations. In contrast to the convention where the programming/erasing gate also acts as the read gate, a dedicated read gate with an oxide-only dielectric is proposed in the new mode. Using the same device under identical programming/erasing conditions, greatly improved programming speed (e.g., 61% increase under the stress condition of 18 V for 10 mu s) is achieved, while the erasing speed, albeit initially retarded, shows enhancement when the erasing time is larger than a certain value, which can be explained by the back-gate bias effects. Retention characterization indicates that the new mode offers a larger memory window after 10 year extrapolation. In addition, a proper auxiliary gate bias applied during programming/erasing processes is found to improve the programming/erasing speed. Finally, by taking advantage of the separate-gated feature, two independent storage sites can be obtained by employing an oxide-nitride-oxide layer as the dielectric for both gates, thus realizing 2-bit/cell functionality. (C) 2011 The Japan Society of Applied Physics
Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices
(2014-06-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chang, Kuo-Pin
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Shih, Yen-Hao
The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.
Modeling the Variability Caused by Random Grain Boundary and Trap-location Induced Asymmetrical Read Behavior for a Tight-pitch Vertical Gate 3D NAND Flash Memory Using Double-Gate Thin-Film Transistor (TFT) Device
(2012-01-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chen, Chih-Ping
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Chang, Kuo-Ping
The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.
Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors
(2009-03-01)
Lin, Horng-Chih
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Hung, Cheng-Hsiung
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Chen, Wei-Chen
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Lin, Zer-Ming
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Hsu, Hsing-Hui
In this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.
Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness
(2009-06-01)
Lin, Horng-Chih
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Chen, Wei-Chen
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Lin, Chuan-Ding
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Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.
Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices
(2011-11-01)
Lin, Horng-Chih
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Lin, Zer-Ming
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Chen, Wei-Chen
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Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.
Real-Time Obstructive Sleep Apnea Detection from Frequency Analysis of EDR and HRV using Lomb Periodogram
(2015)
Fan, Shu-Han
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Chou, Chia-Ching
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Chen, Wei-Chen
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Fang, Wai-Chi
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電機工程學系
In this study, an effective real-time obstructive sleep apnea (OSA) detection method from frequency analysis of ECG-derived respiratory (EDR) and heart rate variability (HRV) is proposed. Compared to traditional Polysomnography (PSG) which needs several physiological signals measured from patients, the proposed OSA detection method just only use ECG signals to determine the time interval of OSA. In order to be feasible to be implemented in hardware to achieve the real-time detection and portable application, the simplified Lomb Periodogram is utilized to perform the frequency analysis of EDR and HRV in this study. The experimental results of this work indicate that the overall accuracy can be effectively increased with values of Specificity (Sp) of 91%, Sensitivity (Se) of 95.7%, and Accuracy of 93.2% by integrating the EDR and HRV indexes.
Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation
(2015-10-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Tsui, Bing-Yue
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Hsieh, Kuang-Yeu
Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry.