Browsing by Author "Chen, Wei-Zen"

Now showing 1 - 20 of 49

A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop Using Delta Sigma Noise-Shaped Phase Detector
(2013-01-01)
Liu, Yao-Chia
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Chen, Wei-Zen
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Chou, Mao-Hsuan
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Tsai, Tsung-Hsien
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Lee, Yen-Wei
A 0.1-3 GHz, cell-based, fractional-N ADPLL with Delta Sigma noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um x 240um.
A 0.4V 53dB SNDR 250 MS/s Time-Based CT Delta Sigma Analog to Digital Converter
(2015-01-01)
Chen, Hung-Kai
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Chen, Wei-Zen
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Ren Zhiyuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time Delta Sigma analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 mu W. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm(2).
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-mu m CMOS Technology
(2011-05-01)
Huang, Shih-Hao
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Chen, Wei-Zen
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Chang, Yu-Wei
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Huang, Yang-Tung
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電子工程學系及電子研究所
This paper describes the design of a 10-Gb/s fully integrated CMOS optical receiver, which consists of a novel spatially-modulated photo detector (SMPD), a low-noise trans-impedance amplifier (TIA), and a post-limiting amplifier on a single chip. The bandwidth of proposed meshed SMPD can be boosted up to 6.9 GHz under a reverse-biased voltage of 14.2 V. The measured responsivity of the meshed SMPD is 29 mA/W as illuminated by 850-nm light source. To compensate the relatively low responsivity of on-chip CMOS photo detector (PD), a high-gain TIA with nested feedback and shunt peaking is proposed to achieve low-noise operation. The optical receiver is capable of delivering 25-k Omega conversion gain when driving 50-Omega output loads. For a PRBS test pattern of 2(7)-1, the 10-Gb/s optoelectronic integrated circuit (OEIC) has optical sensitivity of -6 dBm at a bit-error rate (BER) of 10(-11). Implemented in a generic 0.18-mu m CMOS technology, the chip area is 0.95 mm by 0.8 mm. The trans-impedance amplifier, post amplifier, and output buffer respectively drain 38 mW, 80 mW, and 27 mW from the 1.8-V supply.
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression
(2015-03-01)
Su, Ming-Chiuan
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Chen, Wei-Zen
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Wu, Pei-Si
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Chen, Yu-Hsiang
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Lee, Chao-Cheng
A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI(pp) jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps(rms). The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm(2) only. It dissipates 12.4 mW from 1 V supply.
A 10-Gbps CMOS Single Chip Optical Receiver with 2-D Meshed Spatially-Modulated Light Detector
(2009)
Huang, Shih-Hao
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a 10-Gbps optical receiver with monolithically integrated CMOS photo detector. A trans-impedance amplifier with nested feedback and shunt-peaking is proposed for broad-band and high gain operations. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver is capable of delivering 25 k Omega trans-impedance gain when driving 50 SI output loads. The operating speed is improved by 3X over the prior art with the same technology. Implemented in a generic 0.18-mu m CMOS technology, the chip size is 0.95 mm x 0.8 mm. This receiver core drains 118 mW from 1.8 V supply.
A 10Bit, 10MS/s, Low Power Cyclic ADC
(2013)
Chen, Chien-Hung
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to accelerate conversion speed. At 10 MS/s operation, the corresponding FOM is 0.45pJ/conv.-step. Fabricated in a 85nm CMOS technology, the chip size is 0.077mm(2).
A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression
(2013-01-01)
Su, Ming-Chiuan
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Chen, Wei-Zen
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Wu, Pei-Si
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Chen, Yu-Hsian
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Lee, Chao-Cheng
A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1: 5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI(pp) input data jitter, the recovered clock jitter at 2GHz is 2.94ps(rms). The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200x150 mu m(2).
A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition
(2014-06-01)
Chen, Wei-Zen
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Lu, Tai-You
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Wang, Yan-Ting
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Jian, Jhong-Ting
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Yang, Yi-Hung
A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm(2). The PLL locking time is less than 3 mu s. This chip drains 24 mW from a 1.2 V power supply.
A 2 x 20-Gb/s, 1.2-pJ/bit, Time-Interleaved Optical Receiver in 40-nm CMOS
(2014)
Huang, Shih-Hao
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Hung, Zheng-Hao
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper describes a single-chip, 2 x 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1: 4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 mu A(pp) at bit-error-rate of less than 10(-12). Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm(2).
A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation
(2012-03-01)
Chen, Wei-Zen
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Lu, Tai-You
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Ou, Wei-Wen
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Chou, Shun-Tien
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Yang, Song-Yu
A 2.4 GHz reference-less single chip wireless receiver for 1 Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the RF received signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, postamplifier, and digital demodulator on a single chip, the total power consumption is 20.4 mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -111 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm(2).
A 2.4 GHz Reference-less Wireless Receiver for 1Mbps QPSK Demodulation
(2010)
Chen, Wei-Zen
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Ou, Wei-Wen
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Lu, Tai-You
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Chou, Shun-Tien
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Yang, Song-Yu
A 2.4 GHz reference-less single chip wireless receiver for 1Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the received RF signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power consumption is 20.4mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -112 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm(2).
A 2.5 Gbps CMOS fully integrated optical receicer with lateral PIN detector
(2007)
Chen, Wei-Zen
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Huang, Shih-Hao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mV(pp) to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mu m CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm(2).
A 20-Gb/s Optical Receiver with Integrated Photo Detector in 40-nm CMOS
(2013)
Huang, Shih-Hao
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Chen, Wei-Zen
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dB Omega conversion gain when driving 50-Omega output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 x 0.54 mm(2). This receiver core drains 30 mW from 1-V supply.
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
(2018-01-01)
Lee, Yuan-Sheng
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A single chip optical receiver comprising of a font-end amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 2(31)-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10(-12) (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm(2). It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.
A 25 Gb/s 1.13 pJ/b-10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS
(2017-03-01)
Huang, Shih-Hao
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as 0.35x operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than 10(-12). In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm(2) only.
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
(2019-08-01)
Lee, Yuan-Sheng
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Ho, Wei-Hsiang
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Chen, Wei-Zen
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 231-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm2. The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
(2019-08-01)
Lee, Yuan-Sheng
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Ho, Wei-Hsiang
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Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 2(31)-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm(2). The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
A 25-Gb/s,-10.8-dBm Input Sensitivity, PD-Bandwidth Tolerant CMOS Optical Receiver
(2015)
Huang, Shih-Hao
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper describes a 25-Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current boosting preamplifier with time-interleaved integrating-type optical receiver, it also circumvents CID issue with high PD bandwidth tolerance. Experimental results show that the receiver can achieve 25-Gb/s operation by integrating with a 9-GHz or 17-GHz GaAs PD. Input sensitivities in the two cases are -7.2 dBm (w/i 9-GHz PD) and -10.8 dBm (w/i 17-GHz PD) respectively for BER of less than 10(-12). The energy efficiency is 1.13 pJ/bit. Fabricated in TSMC 40-nm CMOS technology, the core circuit occupies a chip area of 0.007 mm(2) only.
A 3.12 pJ/bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery
(2014)
Hong, Zheng-Hao
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm(2) only.
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
(2015-11-01)
Hong, Zheng-Hao
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Liu, Yao-Chia
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Chen, Wei-Zen
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 19-27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19-27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm(2) only.