A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop Using Delta Sigma Noise-Shaped Phase Detector

Abstract

A 0.1-3 GHz, cell-based, fractional-N ADPLL with Delta Sigma noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um x 240um.