Browsing by Author "Chen, Yin-Nien"

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A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
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Fan, Ming-Long
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Tsai, Ming-Fu
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
(2011)
Yang, Hao-I
;
Yang, Shih-Chi
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Hsia, Mao-Chih
;
Lin, Yung-Wei
;
Lin, Yi-Wei
This paper describes a high-performance low V(MIN) SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V(MIN). A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated.
"Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits"
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
"This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated."
Design and Analysis of Robust Tunneling FET SRAM
(2013-03-01)
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push-pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance.
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
(2013)
Tsai, Ming-Fu
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Fan, Ming-Long
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Pao, Chia-Hao
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at V-DD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising V-trip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.
Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices
(2015)
Wu, Tse-Ching
;
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the hybrid TFET-FinFET 32-bit carry-look-ahead adder (CLA) circuit and compare the delay, power and power-delay product (PDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. In the hybrid design, TFETs are used for the top critical path to reduce the longest path delay, and FinFETs are used for the rest of the circuit to reduce switching power and leakage power. The PDP of the hybrid TFET-FinFET CLA circuit is better than the circuits with all FinFET and all TFET implementations in the vicinity of V-DD=0.3V. However, as the operating voltage is further reduced, the lower-ranked critical paths (e.g. 2nd critical path) with some FinFET devices in the path stick out, and the delay and PDP become inferior to all TFET implementation.
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
(2015)
Wu, Tse-Ching
;
Chen, Chien-Ju
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Chen, Yin-Nien
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage (CMOS)-M-2 latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
(2014-12-01)
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, V-min and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across V-DD = 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation.
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
(2014-12-01)
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low V-T hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at V-DD = 0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed.
Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness
(2015)
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we comprehensively investigate the impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-look-ahead adder (CLA) circuits operating in near-threshold region using atomistic 3D TCAD mixed-mode simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that at low operating voltage (<0.3V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET even with the impacts of random variations. As the operating voltage decreases, the performance advantage of TFET CLA becomes more significant due to its better I-on and C-g,C-ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse I-off variability of TFET devices.
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
(2017-01-01)
Chang, Chia-Ning
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Chen, Yin-Nien
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Huang, Po-Tsang
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Su, Pin
;
Chuang, Ching-Te
This paper investigates and evaluates analog and digital low-dropout linear voltage regulators (LDO) with FinFET, TFET and hybrid TFET-FinFET implementations. We utilize Sentaurus physics-based atomistic 3D TCAD mixed-mode simulations for device characteristics and HSPICE with look-up tables based on Verilog-A models calibrated with TCAD simulation results. Frequency response, load regulation and power supply rejection ratio (PSRR) are evaluated for analog LDOs under low, medium and high bias-current conditions. The results indicate that for analog implementations, TFET-LDO and hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under low and medium operating currents, whereas at higher operating current, FinFET implementation would outperform. As operating voltage is reduced, the performances of analog implementations degrade, and digital implementations become favorable for VIN below around 0.55V. We further show that for digital LDO, all FinFET implementation provides superior performance over all TFET and hybrid TFET-FinFET implementations.
Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
(2017-01-01)
Tu, Meng-Hsuan
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Chen, Yin-Nien
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Su, Pin
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Chuang, Ching-Te
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電子工程學系及電子研究所
In this paper, we investigate the hybrid TFET-FinFET implementation of ternary content addressable memory (TCAM) and compare the search time, power and energy with all FinFET and all TFET implementations in near-threshold region using atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The TCAM utilizes a don't-care-based ripple search line (SL) to improve the search performance and power. In the hybrid design, TFETs are used for comparison circuit to improve the performance and energy of serially connected match line (ML) at low voltage, while FinFETs are used for the rest of the circuit for better cell stability, switching power and leakage power.
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
(2012)
Yang, Hao-I
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Lin, Yi-Wei
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Hsia, Mao-Chih
;
Lin, Geng-Cing
;
Chang, Chi-Shin
This paper presents a 1.0Mb high-performance 0.6V V-MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.
Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits
(2012)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single trap induced Random Telegraph Noise (RTN) on scaled FiriFET devices in tied-gate and independent-gate modes, 6T SRAM cell and logic circuits. The dependence of RTN amplitude on trap location, EOT and temperature is evaluated through 3D atomistic TCAD simulations. It is observed that charged trap located near the bottom of sidewall (gate) interface, in the middle region between the source/drain results in most significant impact. EOT scaling and higher temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependency on the location of the trap and current conduction path are analyzed. We show that planar BULK device, with larger Subthreshold Swing (S.S.) and comparable trap-induced V-T shift (Delta V-T), exhibits less nominal RTN degradation than FinFET for trap placed in the worst position. However, the larger variability and surface conduction characteristic of planar BULK device result in broader dispersion and larger worst-case degradation than FinFET with smaller variability and volume conduction inside the silicon fin. For FiriFET 6T SRAM cell, the READ Static Noise Margin (RSNM) of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the relative importance of RTN on the cell stability increases. The leakage/delay of FinFET inverter, 2-Way NAND and 2-To-1 multiplexer are investigated using mixed-mode TCAD simulations. The existence of RTN is found to cause similar to 24-27% and 13-15% variation in leakage and delay at V-dd=0.4V, respectively, for the logic circuits evaluated.
Impacts of Single Trap Induced Random Telegraph Noise on FinFET Devices and SRAM Cell Stability
(2011)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
In this work, we investigate, for the first time, the impacts of single trap induced Random Telegraph Noise (RTN) on the drain current of FinFET devices and the stability of FinFET 6T SRAM cell. For FinFET operating in tied-gate mode, we show that the charged trap located near the bottom of the sidewall channel. a the middle of the channel between source/drain results in most significant impact (worst position). In independent-gate mode, degraded RTN is observed and depends on the relative location of the trap and current conduction path. In addition, our results indicate that the correlation between RTN and fine Line Edge Roughness (fin LER) and Work Function Variation (WFV) is not obvious as compared with the BULK counterpart. For 6T SRAM operating in subthreshold region, single charged trap for each individual cell transistor, placed at the worst position, forms 64 possible combinations and the resulting extreme values of cell stability during READ and WRITE operations are examined for various V(dd). Because of the reduced carries with decreasing supply voltage, the relative importance of RTN on cell stability increases and hinders the cell stability of subthreshold 6T SRAM cell in the vicinity of distribution tail.
Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits
(2013)
Yang, Shao-Yu
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Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on the drain current, stability of 6T SRAM cells and logic circuits of Si and Ge NanoWire (NW) FETs. The trap position dependence of the RTN amplitude (Delta Ids/Ids) along the channel length direction is examined. For Si-NW FET, significant RTN impact is observed for trap located near the middle region of channel between the source/drain (worst position), while for Ge-NW FET, the worst position depends on the drain bias (Vds) and gate bias (Vgs). The RTN amplitude of Ge-NW FET exhibits distinctly different Vgs and Vds dependence compared with the Si-NW FET due to lower bandgap, higher permittivity, and band-to-band tunneling at the drain in Ge-NW FET. In particular, it is found that Ge-NW FET may exhibit negative RTN amplitude (Ids increases) with acceptor type trap due to the reduction of band-to-band tunneling length when the trap is located near the drain. Ge-NW FET shows larger Vdd dependence of the RTN amplitude variation. For 6T NW SRAM cell, the READ Static Noise Noise Margin (RSNM) of 64 combinations from trapping/de-trapping state in each cell transistor is examined. The impact of RTN on the leakage of NW inverter is investigated using 3D atomistic TCAD mixed-mode simulations.
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
(2014)
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on ION and IOFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.
Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling
(2014-01-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.
Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers
(2013)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of Random Telegraph Noise (RTN) caused by a single acceptor-type trap on Tunnel FET (TFET) based devices, 8T SRAM cell and sense amplifiers. 3D atomistic TCAD simulations accounting for the impact of localized/negatively-charged trap are utilized to assess the dependence of RTN amplitude (Delta I-D/I-D) on trap location and device geometry. Our results indicate that significant RTN impact occurs for trap located near the tunneling junction. The device design strategies (thinner EOT, W-fin and longer L-eff) to improve TFET device characteristics are found to increase the susceptibility to RTN. Furthermore, TFET-based standard 8T SRAM cell and several commonly used sense amplifiers including Current Latch Sense Amplifier (CLSA), Voltage Latch Sense Amplifier (VLSA), and single-ended large-signal inverter sense amplifier are examined using atomistic 3D TCAD mixed-mode simulations. The presence of RTN is shown to cause extra similar to 16% variations in cell stability (at V-dd = 0.3V) and additional similar to 80mV variation in offset voltage for sense amplifiers at V-dd = 0.5V.