Browsing by Author "Chen, Ying-Chieh"

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Doping profile and Ge-dose optimization for silicon-germanium heterojunction bipolar transistors
(2009-10-01)
Li, Yiming
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Chen, Ying-Chieh
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Hwang, Chih-Hong
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傳播研究所
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電子工程學系及電子研究所
The speed of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) has been dramatically increased. It is known that the speed of HBTs is dominated by the base transit time, which could be influenced by the doping profile in the base region and the Ge concentration. In this study, the design of the doping profile and Ge-dose concentration for SiGe HBTs are mathematically formulated and solved by a technique of geometric programming ( GP). The solution calculated by the GP method is guaranteed to be a global optimal. The accuracy of the adopted numerical optimization technique is first confirmed by comparing with two-dimensional device simulation. The result of this study shows that a 23% Ge fraction may maximize the current gain; furthermore, a 12.5% Ge may maximize the cut-off frequency for the explored device, where a 254 GHz cut-off frequency is achieved.
Geometric programming approach to doping profile design optimization of metal-oxide-semiconductor devices
(2013-07-01)
Li, Yiming
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Chen, Ying-Chieh
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交大名義發表
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資訊工程學系
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National Chiao Tung University
We study one-dimensional doping profile design optimization problem of metal-oxide-semiconductor (MOS) devices using a geometric programming (GP) technique. To model the explored optimal doping profile into a GP problem, the subthreshold swing is formulated as an objective function and the on- and off-state currents are considered as constraints for solving the corresponding optimal doping profile. The GP problem is a special type of convex optimization and is solved globally and efficiently using the existing numerical solvers in GGPLAB. The accuracy of optimized results is validated by comparing with numerical semiconductor device simulation. This approach provides a way to optimize doping problem which may benefit manufacturing of MOS devices. (C) 2012 Elsevier Ltd. All rights reserved.
Growth of high-aspect-ratio gold nanowires on silicon by surfactant-assisted galvanic reductions
(2008-06-03)
Huang, Ting-Kai
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Chen, Ying-Chieh
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Ko, Hsin-Chun
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Huang, Hsin-Wei
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Wang, Chia-Hsin
A simple galvanic reduction for direct growth of An nanowires on silicon wafers is developed. The nanowires were prepared by reacting HAuCl4(aq) with Sn-(s) in the presence of CTAC((aq)) (cetyltrimethylammonium chloride) and NaNO3(aq), which were important to the product morphology development. The nanowire diameter was 50-100 nm, and the length was more than 20 mu m.
High frequency property optimization of heterojunction bipolar transistors using geometric programming
(2007)
Li, Yiming
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Chen, Ying-Chieh
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電信工程研究所
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Institute of Communications Engineering
In this work, we theoretically optimize the high frequency property of silicon-germanium heterojunction bipolar transistors (HBTs) using a geometry programming (GP) technique. It is known that the base transit time of semiconductor devices potentially is a function of doping profile, device geometry and materials which significantly dominate the high frequency properly of HBTs. To maximize the cut-off frequency of HBTs, the subject is formulated as a GP optimization problem by physically considering the base transit time as an object function. The GP model is solved numerically so that the cutoff frequency of HBT could be optimized for specified upper and lower bounds of the base doping concentration, and certain Ge composition. This work also shows that for 13% Ge profile, the cut-off frequency may reach a maximal value.
Inverse Doping Profile of MOSFETs via Geometric Programming
(2012)
Li, Yiming
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Chen, Ying-Chieh
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電機工程學系
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Department of Electrical and Computer Engineering
In this study, we optimize one-dimensional doping profiles between the interface of semiconductor and oxide to the substrate in metal-oxide-semiconductor field-effect transistors (MOSFETs). For a set of given current-voltage curves, the problem is modelled as a geometric programming (GP) problem. The MOSFET\'s DC characteristics including the on-and off-state currents are simultaneously derived as functions of the doping profile in the GP problem.
Optimal Doping Profile of MOSFETs Using Geometric Programming
(2009)
Chen, Ying-Chieh
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Li, Yiming
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電信工程研究所
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Institute of Communications Engineering
This study employs a novel geometric programming technique to optimize the doping profile of metal semiconductor oxide field effect transistor (MOSFET) subject to specified device characteristics, such as the threshold voltage, the on- and off-state currents and the subthreshold swing. The optimal design of doping profiles for MOSFET devices is for the first time formulated as a geometric programming problem. This special type of optimization problems can be transformed into a convex optimization problem, and therefore can be solved globally and efficiently. For targeting a designed threshold voltage as well as obtaining a high transconductance, the doping distribution of an examined MOSFET device is extracted. Consequently, various constrains of DC characteristics are estimated to obtain the desired doping profile. The approach provides an alternative way to accelerate the design of doping profile process and benefits the manufacturing of MOS devices.
Preservation of evidence in case of online gaming crime
(2008)
Chen, Patrick S.
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Hung, Cheng-Yu
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Ko, Chiao-Hsin
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Chen, Ying-Chieh
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資訊管理與財務金融系註：原資管所+財金所
Along with the rapid growth of network applications and digital contents, online gaming has become a very successful industry in recent years. It not only brings tremendous business opportunities but also attracts marvelous customers to be online players. However, due to the lack of virtual property protection and related information security schemes, more and more players have violated the law because of its real world profit. Unfortunately, online gaming crime has turned out one of the most serious cybercrimes in many countries, such as in Taiwan, South Korea, China, and so on. In order to solve this judicial problem and effectively protect virtual property, we propose a Virtual Property Description Language (VPDL) as the syntax to record and express virtual property. There are six models, including Identity Model, Ownership Model, Trading Model, Content Model, Revocation Model, and Security Model. It can effectively protect virtual property and strengthen the competence of digital evidence by recording the legal source, ownership, trading track, and handling of virtual properties so as to lower the cases of online gaming crime. The online gaming companies may use it in the aspects of virtual property management, tracing historic records and collecting legal digital evidence, while the existing system mechanism of online game doesn\'t need to be changed.
Temperature Aware Floorplanning via Geometry Programming
(2008)
Li, Yiming
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Chen, Ying-Chieh
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Cheng, Hui-Wen
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電信工程研究所
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Institute of Communications Engineering
Power density of microprocessors is increasing with every new process generation resulting in increasingly higher chip temperatures. The high temperature of the chip greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling solutions significantly more expensive. The maximum temperature of a block in a chip depends, however, not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) method for the minimum temperature and area floorplanning problem. We notice that it is a nonlinear convex problem and its optimal solution can be obtained by GP method. The numerical result shows that the difference between the original temperatures and temperatures for MCNC ami33 after optimization can be as high as 80 degrees C. We have modified a floorplanning tool to include temperature as an objective for block area to reduce the hot spot temperature. We show that it is possible to find a floorplan that can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance.
Temperature-aware floorplanning via geometric programming
(2010-04-01)
Chen, Ying-Chieh
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Li, Yiming
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傳播研究所
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電機工程學系
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Institute of Communication Studies
With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 degrees C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 degrees C to 10 degrees C, where the minimized chip area is about 700 mm(2). For the case of MCNC ami49, the maximum temperature reduction is 60 degrees C (i.e., its reduction is from 65 degrees C to 5 degrees C) with a minimal chip area of 2500 mm(2). We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously. (C) 2009 Elsevier Ltd. All rights reserved.