Browsing by Author "Chen, Yu-Yu"

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Device Simulation-Based Multiobjective Evolutionary Algorithm for Process Optimization of Semiconductor Solar Cells
(2013-07-03)
Li, Yiming
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Chen, Yu-Yu
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Chen, Chieh-Yang
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Shen, Cheng-Han
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Cheng, Hui-Wen
This article implements for the first time a numerical semiconductor device simulation-based multiobjective evolutionary algorithm (MOEA) for the characteristic optimization of amorphous silicon thin-film solar cells, based upon a unified optimization framework (UOF). To calculate the device's characteristic, a set of coupled solar cell transport equations consisting of the Poisson equation, the electron-hole current continuity equations, and the photo-generation model is solved numerically. Electrical characteristics, the short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated to analyze the properties of the explored solar cells. The aforementioned device simulation results are used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm (NSGA-II) in the UOF. Notably, designing parameters including the material and structural parameters, and the doping concentrations are simultaneously optimized for the explored solar cells. The simulation-based MOEA methodology is useful in optimal structure design and manufacturing of semiconductor solar cells.
Experimentally Effective Clean Process to C-V Characteristic Variation Reduction of HKMG MOS Devices
(2013)
Chen, Chien-Hung
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Li, Yiming
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Chen, Chieh-Yang
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Chen, Yu-Yu
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Hsu, Sheng-Chia
In this work, the planar HKMG MOS devices are fabricated on (100) wafer with p-substrate. To improve the samples\' interface roughness between the Si/Ge film and the interface layer, three different clean treatments are considered to fabricate the MOS devices. Among processes, the experiment indicates that HF and water rinse can present hydrogen termination to bond silicon as a good passivation. The measured C-V curves and HRTEM of the fabricated samples show the interface roughness is improved significantly. The extracted shift of flat band voltage (Delta V-fb) and density of interface traps (D-it) have around 50% improvement.
Mobility model extraction for surface roughness of SiGe along (110) and (100) Orientations in HKMG bulk FinFET devices
(2013-09-01)
Chen, Chien-Hung
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Li, Yiming
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Chen, Chieh-Yang
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Chen, Yu-Yu
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Hsu, Sheng-Chia
In this work, the FinFET HKMG MOS devices are fabricated on silicon wafer with p-substrate. The interface roughness between the SiGe and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. (C) 2013 Elsevier B.V. All rights reserved.
Multi-Objective Display Panel Design Optimization using Circuit Simulation-Based Evolutionary Algorithm
(2012)
Chen, Yu-Yu
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Li, Yiming
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Chen, Chieh-Yang
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Chiang, Chien-Hshueh
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傳播研究所
We for the first time implement a multi-objective evolutionary algorithm (MOEA) to optimize the display panel gate driver circuits with amorphous silicon thin-film transistors (ASG driver circuit). The MOEA is integrated with a circuit simulator based upon a unified optimization framework. The results of this study indicate the developed optimization flow can find the better solutions than a simple GA. The measurement data of the fabricated sample further show the achieved result is robust and superior to the original design. This approach benefits design and manufacturing of display panels in the industry of information and communications technology.
On Characteristic Variability of 16-nm-Gate Bulk FinFET Devices Induced by Intrinsic Parameter Fluctuation and Process Variation Effect
(2013-01-01)
Chen, Chieh-Yang
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Li, Yiming
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Chen, Yu-Yu
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Chang, Han-Tung
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Hsu, Sheng-Chia
On Statistical Variation of MOSFETs Induced by Random-Discrete-Dopants and Random-Interface-Traps
(2012)
Li, Yiming
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Su, Hsin-Wen
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Chen, Chieh-Yang
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Cheng, Hui-Wen
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Chen, Yu-Yu
In this work, we statistically study characteristic fluctuation of 16-nm-gate high-kappa/metal gate (HKMG) MOSFETs by random-discrete-dopants (RDDs) inside silicon channel and random-interface-traps (RITs) at high-kappa/silicon interface. Randomly generated devices with three-dimensional (3D) RDDs inside device channel and 2D RITs at HfO2/Si interface are incorporated into quantum mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to RITs near the source and drain ends, and RDDs near the device channel surface and silicon substrate. Characteristic fluctuations are affected to different extents by the random combinatorial RDDs and RITs. Nonlinearly correlated RDDs and RITs further violate the statistical assumption of independent identical distributions between the RDDs- and RITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is less than their statistical sum due to local interaction of surface potentials resulting from the RDDs and RITs simultaneously. In contrast to RDDs fluctuation, the screening effect of device\'s inversion layer cannot effectively screen potential\'s variation resulting from RITs; thus, devices still have noticeable gate capacitance characteristic fluctuation under high gate bias.
Random Work Function Induced DC Characteristic Fluctuation in 16-nm High-kappa/Metal Gate Bulk and SOI FinFETs
(2012)
Su, Hsin-Wen
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Chen, Yu-Yu
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Chen, Chieh-Yang
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Cheng, Hui-Wen
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Chang, Han-Tung
This work studies the metal gate\'s work function fluctuation induced DC characteristic fluctuation in the 16-nm bulk and silicon-on-insulator (SOI) fm-type field effect transistor (FinFET) devices using an experimentally calibrated 3D device simulation. The method of localized work function fluctuation simulation enables us to estimate local fluctuations including the nanosized grain\'s random effects of FinFET with TiN/HfO2 gate stacks. The result of this study shows characteristic fluctuation strongly depends upon the size of localized nanosized metal grains. The shape of grains does have marginal influence on device\'s variability.
Random-work-function-induced characteristic fluctuation in 16-nm-gate bulk and SOI FinFETs
(2014-01-01)
Li, Yiming
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Chen, Chieh-Yang
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Chen, Yu-Yu
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資訊工程學系
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Department of Computer Science
In this paper, we, for the first time, study the metal gate\'s work-function-fluctuation-induced variability in the 16-nm-gate bulk and silicon on insulator (SOI) fin-type field effect transistor (FinFET) devices using an experimentally calibrated 3D device simulation. According to metal\'s property, random nanosized grains of titanium nitride (TiN) gate are statistically positioned in the gate region to examine the associated electrostatic potential and carrier transportation characteristics, concurrently capturing fluctuations resulting from nanosized grain\'s random number, position and size effects. The newly advanced methodology of localised work function fluctuation simulation enables us to estimate characteristic fluctuations and to examine the nanosized grain\'s random effects for the 16-nm-gate bulk and SOI FinFETs with TiN/HfO2 gate stacks with respect to the aspect ratio (AR = fin height/fin width) of two. The results of this study show that the DC characteristic fluctuation of FinFET devices strongly depends on the high and low work functions of localised nanosized metal grains. The threshold voltage (V-th) varies with the number of grain sizes and the V-th\'s fluctuation (sigma V-th) is suppressed as the grain size is minimised. sigma V-th of SOI FinFET (about 9.7 mV) is about 1.5 times smaller than that with bulk FinFET (about 14.6 mV). Furthermore, sigma V-th of SOI FinFET with minimal metal grain\'s size of 2 x 2 nm(2) can be reduced about 23%, compared with the result of bulk one.
Statistical Device Simulation of Intrinsic Parameter Fluctuation in 16-nm-Gate N- and P-type Bulk FinFETs
(2013-01-01)
Chen, Yu-Yu
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Huang, Wen-Tsung
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Hsu, Sheng-Chia
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Chang, Han-Tung
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Chen, Chieh-Yang
In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-kappa / metal gate n- and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations\' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.
The intrinsic parameter fluctuation on high-kappa/metal gate bulk FinFET devices
(2013-09-01)
Li, Yiming
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Su, Hsin-Wen
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Chen, Yu-Yu
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Hsu, Sheng-Chia
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Huang, Wen-Tsung
In this work, based on the experimentally calibrated 3D device simulation, we for the first time estimate the impact of intrinsic parameter fluctuation on the electrical characteristic of 16-nm-gate TiN/HfO2 bulk FinFETs. The sources of intrinsic parameter fluctuation include the random discrete dopants, interface traps and work function differences, simultaneously. The full 3D simulated threshold voltage fluctuation, induced by the aforementioned random sources simultaneously, is 26.2 mV for the N-type bulk FinFET (and is 55.5 mV for the planar N-MOSFET). For the N-type bulk FinFE'T, the statistical sum of these fluctuations is 9.5% (and is 12.3% for the planar device) overestimation, compared with the full 3D simulation. One of the main reasons is the independence assumption on these random variables is destroyed owing to interactions to different extents among RDs, ITs and WKs. The coupled surface potentials cannot be simply estimated by using their statistical sum of individual random source. Under the same threshold voltage, compared with the result of the planar MOSFETs, more than 50% reduction on the threshold voltage fluctuation of the explored bulk FinFETs is observed owing to the benefit of 3D structural nature. (C) 2013 Elsevier B.V. All rights reserved.
Upper/lower-side random dopant fluctuation on 16-nm-gate HKMG bulk FinFET
(2015-01-01)
Li, Yiming
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Huang, Wen-Tsung
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Chen, Chieh-Yang
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Chen, Yu-Yu
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資訊工程學系
In this work, we for the first time classify dopants that exist near the source/drain side or the upper/lower side of silicon fin and explore the impact of random dopants\' (RDs) position on devices\' DC characteristic. The effects of random dopant fluctuation (RDF) on the performance of 16-nm-gate HKMG bulk FinFET are studied by using experimentally validated three-dimensional RDF device simulation. The dopants near the source side or the upper fin would induce large barrier for electrons, so the threshold voltage (Vth) will be increased in n-type HKMG bulk FinFET devices which have more dopants on the source side or the upper fin. In addition, the upper-fin\'s dopants are discovered to have larger influence on the profile of energy band. Moreover, the issue about Vth\'s fluctuation on both the planar MOSFET and the bulk FinFETs with different aspect ratios (AR) is studied. The higher-AR HKMG bulk FinFET devices have relatively smaller Vth\'s variation induced by RDF.