Browsing by Author "Chen, Zong-Yi"

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A 5.8 mW Continuous-Time Delta Sigma Modulator With 20 MHz Bandwidth Using Time-Domain Flash Quantizer
(2015-12-01)
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents a power-efficient realization of a third-order continuous-time delta-sigma (CT - Delta Sigma) modulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The CT - Delta Sigma modulator uses the TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in CMOS 90 nm process. The proposed CT - Delta Sigma modulator consumes 5.8 mW from 1.0 V and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in FOM_W = 96.3 fJ/level and FOM_S = 161 dB.
A Continuous-Time Delta-Sigma Modulator with Novel Data-Weighted Averaging Algorithm for Audio Application
(2015)
Lin, Jia-Ni
;
Chu, Hsing-Chien
;
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機學院
A 4-bit continuous-time delta-sigma modulator (CT-DSM) with the proposed data-weighted averaging (DWA) algorithm for audio application is presented. The proposed method randomly adds one to pointer address in the DWA to reduce distortion tones and improve the performance of spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR), as compared with the conventional DWA. The post-layout simulation results show that the modulator designed in TSMC 0.18 mu m CMOS process achieves the SNDR of 81.5 dB and the dynamic range (DR) of 85dB in 24 kHz signal bandwidth. The chip area is 1.168 x 0.632 mm(2) and the power consumption is 339 mu W from a 1.8 V power supply.
A Fourth-Order FeedForward Continuous-Time Delta-Sigma ADC with 3MHz Bandwidth
(2010)
Huang, Sheng-Wen
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Chen, Zong-Yi
;
Hung, Chung-Chih
;
Chen, Chia-Min
;
電機工程學系
A fourth-order feedforward continuous-time (CT) delta-sigma modulator is presented. The modulator takes an active-RC OpAmp as the first stage because of the high-linearity requirement, and the other three stages are composed by Gm-C integrators. In feedforward topology, a higher out-of-band NTF gain could be taken for better performance. As we know, the most important part in the feedforward CT Delta Sigma modulator is the summation circuit for the feedforward paths. The modulator uses a tuning adder, which we propose, to make sure the modulator can work correctly even under the influence of the process variation on resistors. Finally, the delta-sigma modulator is implemented in standard digital 0.18-mu m CMOS process, which achieves 57.84 dB SNDR over a 3MHz signal bandwidth at an OSR of 16.67. The power consumption of the CT delta-sigma modulator is 11.8 mW from the 1.8-V supply.
A Novel 12-bit Current-Steering DAC with Two Reference Currents
(2015)
Chou, Fang-Ting
;
Chen, Zong-Yi
;
Chu, Hsing-Chien
;
Hung, Chung-Chih
;
電機學院
This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design is compact and consumes low static power. The active area of the 12-bit DAC is 0.36mm(2) approximately. This chip was fabricated by a standard 0.18 mu m CMOS technology, and consumes 38mW at 180MS/s update rate with 1.8V supply voltage.
A Novel Glitch Reduction Circuitry for Binary-Weighted DAC
(2014-01-01)
Chou, Fang-Ting
;
Chen, Chia-Min
;
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機資訊學士班
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm(2) core area, and dissipates 19mW from a single 1.8V power supply.
DLL-Based Pulse-Width Modulation Digital-to-Analog Converter for Continuous-Time Sigma Delta Modulators
(2014-01-01)
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
In this paper, the DLL-based pulse-width modulation (PWM) digital-to-analog converter (DAC) is proposed to convert the output of multi-bit quantizer to a single-bit pulse-width modulated signal in the modified continuous-time sigma-delta modulators (CT-SDMs) with improved signal transfer function (STF). The DLL-based PWM DAC is more robust to clock jitter and excess loop delay (ELD) effects than conventional multi-bit DAC and other PWM DAC with similar speed and power requirements of the integrators in CT-SDMs. Furthermore, the proposed PWM DAC is based on inherently linear single-bit DAC, so the dynamic-element matching (DEM) techniques, which increase the circuit complexity and power consumption to compensate the mismatch of unit elements in the multi-bit DAC, can be removed in CT-SDMs.
Jitter Compensation Technique for Continuous-Time Sigma-Delta Modulator
(2014-01-01)
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-Sigma Delta) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-Sigma Delta modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.
Surface defect engineering: gigantic enhancement in the optical and gas detection ability of metal oxide sensor
(2016-01-01)
Wang, Wen-Chieh
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Lai, Chun-Yen
;
Lin, Yu-Ting
;
Yua, Tzu-Hsuan
;
Chen, Zong-Yi
In this work, the detection ability of nanosensors can be improved extraordinarily via surface defect engineering. A kinked SnO2-X/SnO2 nanostructure was fabricated by tuning the oxygen flow, and this kinked SnO2-X/SnO2 nanostructure was used to study the mechanism of surface defect (oxygen vacancy, V-O) effects via electric measurements. For UV light sensing, the response of the SnO2-X NW device is always better than the SnO2 NW device, and is two orders higher under pure O-2 surrounding conditions. The detection mechanism can be clarified by changing the detection environment (oxygen concentration) and the UV light detection sensitivity can be improved by increasing the surface V-O density. Furthermore, the SnO2-X NW device is very sensitive to its surrounding environment due to the high surface V-O density. Hence, CO/O-2 alternate-detection was used to verify our hypothesis; the results show that the SnO2-X NW device presents great detection abilities, compared with the SnO2 NW device. The sensitivity of the SnO2-X NW device is two orders higher and the reset/response time is faster, compared with the SnO2 NW device. To verify this hypothesis, the polycrystalline structure was fabricated to prove that the detection ability of metal oxide nanosensors can be improved gigantically by increasing surface defect amounts.