Browsing by Author "Chiang, Pai-Tse"

Now showing 1 - 3 of 3

A QFHD 30-frames/s HEVC Decoder Design
(2016-04)
Chiang, Pai-Tse
;
Ting, Yi-Ching
;
Chen, Hsuan-Ku
;
Jou, Shiau-Yu
;
Chen, I-Wen
The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the 64x64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16 x 16 block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a 4x4 block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported 4096x2160
A Reconfigurable Inverse Transform Architecture Design for HEVC Decoder
(2013)
Chiang, Pai-Tse
;
Chang, Tian Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a reconfigurable hardware design which can support the inverse transform size from 4x4 to 32x32 in HEVC (High Efficiency Video Coding). We explore the coefficient properties of various inverse transforms such that a base inverse transform unit can be reconfigured or refined to generate other size of inverse transform. The implementation in 90nm technology can support 3840x2160@30fps processing and only needs about 133.8K gate count, which can save 53% of gate count when compared with previous work.
Fast Zero Block Detection and Early CU Termination for HEVC Video Coding
(2013)
Chiang, Pai-Tse
;
Chang, Tian Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposed a fast zero block detection for various transform size from 32x32 to 4x4 in the new generation of the High Efficiency Video Coding (HEVC) standard. The derivation is based on sum-of-absolute-difference (SAD) value available in the inter prediction computation. The proposed method achieves detection accuracy to 90% in average, and saves transform unit computation by 44% (QP at 22) and 65% (QP at 32) with negligible coding performance loss, when compared with that of HM4.0rc1. Additionally, this pre-skip detection could further help decide the CU inter mode efficiently with about 50% time saving.