Browsing by Author "Chin, CY"

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A novel fully CMOS process compatible PREM for SOC applications
(2005-03-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.
An endurance evaluation method for flash EEPROM
(2004-05-01)
Zous, NK
;
Chen, YJ
;
Chin, CY
;
Tsai, WJ
;
Lu, TC
Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V-T rollup, and cycling V-T window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V-T rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted Delta V-T degradation slope during constant FN stress can be applied quantitatively to predict the V-T window closure during Flash cell cycling.