Browsing by Author "Chin, Chun-Chieh"

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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
(2016-12)
Lin, Jer-Yi
;
Kuo, Po-Yi
;
Lin, Ko-Li
;
Chin, Chun-Chieh
;
Chao, Tien-Sheng
In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 degrees C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing similar to 75 mV/decade, low drain-induced barrier lowering similar to 33 mV/V, and high on/off currents ratio (I-ON/I-OFF) similar to 7 x 10(6) can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.
Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit
(2018-02-01)
Chung, Chris Chun-Chih
;
Shen, Chiuan-Huei
;
Lin, Jer-Yi
;
Chin, Chun-Chieh
;
Chao, Tien-Sheng
We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high-k metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.