Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application

Abstract

In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 degrees C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing similar to 75 mV/decade, low drain-induced barrier lowering similar to 33 mV/V, and high on/off currents ratio (I-ON/I-OFF) similar to 7 x 10(6) can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.