Browsing by Author "Chiueh, Herming"

Now showing 1 - 20 of 49

A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-01-01)
Tang, Kea-Tiong
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Chiu, Shih-Wen
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Shih, Chung-Hung
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Chang, Chia-Ling
;
Yang, Chia-Min
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip
(2018-10-01)
Chou, Ting-I
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Chang, Kwuang-Han
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Jhang, Jia-Yin
;
Chiu, Shih-Wen
;
Wang, Guoxing
Miniature gas detection system is desirable for many applications. In this brief, we propose a fully integrated nose-on-a-chip for mobile phones and wearable devices. The chip has 36 on-chip sensors, a 36-channel adaptive interface with an integrated programmable amplifier, a four-channel frequency readout interface, one on-chip temperature sensor, a successive approximation analog-to-digital converter, a scalable learning kernel cluster, and a reduced instruction set computing core with low-voltage static random-access memory. This chip is fabricated using the TSMC 180-nm CMOS process and consumes 2.6 mW at 1 V. on-chip temperature and humidity sensors are included in this system for acquiring environmental information. An environmental compensation algorithm based on common principal components analysis is also implemented for high-accuracy odor classification. This fully integrated nose-on-a-chip provides promising results for odor detection and classification for use in mobile and wearable device applications.
A 36-mW 320-MHz CMOS Continuous-Time Sigma-Delta Modulator with 10-MHz Bandwidth and 12-bit Resolution
(2010)
Hong, Kuo-Che
;
Chiueh, Herming
;
傳播研究所
;
Institute of Communication Studies
A wide-bandwidth low-power CT Sigma Delta modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 mu m CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.
A 36-mW Continuous-Time Sigma-Delta Modulator with 74db Dynamic Range and 10-MHz Bandwidth
(2010)
Hong, Kuo-Che
;
Chiueh, Herming
;
電機工程學系
;
Department of Electrical and Computer Engineering
A wide-bandwidth low-power CT Sigma Delta modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 mu m CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time deviator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.
A 53.4-mu W CMOS Temperature Sensor with an Inaccuracy of +/- 1.9 degrees C (3 sigma) from-65 degrees C to 165 degrees C
(2011)
Lee, Mitchell Sheng-Cheng
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Chen, Teng-Cheng
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Liou, Chia-Yi
;
Chiueh, Herming
;
電機工程學系
A 53.4-mu W CMOS temperature sensor with a 3 sigma inaccuracy of +/- 1.9 degrees C from -65 degrees C to 165 degrees C is designed and implemented in TSMC 0.18um CMOS technology. The proposed temperature sensor includes a pure-CMOS PTAT circuitry, a pre-amplifier and a low-power Sigma-Delta ADC. The proposed PATA circuit utilized temperature compensation technology to enhance the linearity. This circuit has widest temperature range compare to other designs, which is suitable to be utilized to electronic devices in extreme temperature condition.
A 69 mu W CMOS Smart Temperature Sensor with an Inaccuracy of +/- 0.8 degrees C (3 sigma) from-50 degrees C to 150 degrees C
(2012)
Lee, Sheng-Cheng
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Chiueh, Herming
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
A proposed temperature sensor is based on pure CMOS PTAT circuitry, a preamplifier and a sigma delta ADC capable of simple and efficient temperature sensor conversion to digital value. The designed PTAT circuit utilized temperature compensation technology to enhance the linearity. The temperature sensor, which occupies 0.475 mm(2), is fabricated using the TSMC 0.18 mu m one-poly six-metal (1P6M) process. Measurement results show that the senor consume 46uA with a 1.5 V supply at 100 sample/s at room temperature. The sensor operates from -50 degrees C to 150 degrees C, archiving a 3 sigma resolution of +/- 0.8 degrees C.
A CMOS Bio-Inspired 2-D Motion Direction Sensor Based on a Direction Computation Method Derived From the Directionally Selective Ganglion Cells in the Retina
(2011-12-01)
Yang, Wen-Chia
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Lin, Li-Ju
;
Chiueh, Herming
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
A CMOS bio-inspired motion direction sensor structure and its associated computation method are proposed. Both method and structure with excitation-inhibition operation are derived from the directionally selective ganglion cells (DSGCs) in the retina to mimic their functions. Edge-number normalization for direction calculation and pseudo-random tessellation (PRT) structure for pixel layout arrangement are also proposed to enhance the accuracy of the computation. An experimental chip based on the proposed method and structure has been designed, fabricated, and measured. The chip comprised 32 x 32 pixels with a pixel size of 63 x 63 mu m(2) and a fill factor of 12.8%. The total chip size is 3.3 x 4.2 mm(2) and the power consumption is 9.9 mW in the dark and 21 mW at a maximum clock rate of 10 MHz with 3.3-V power supply. The fabricated chip has been measured with different moving patterns, and a computation error of less than 11 degrees has been accomplished. This verifies the correct functions of the proposed motion direction sensor. With the capability of real-time motion detection and processing under low power dissipation, the proposed sensor is feasible for many applications.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
(2014-01-01)
Chen, Wei-Ming
;
Chiueh, Herming
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Chen, Tsan-Jieh
;
Ho, Chia-Lun
;
Jeng, Chi
An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wire-less power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30-mu A stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18-mu m CMOS and occupies 13.47 mm(2). Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy 92% within 0.8 s.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
(2013-01-01)
Chen, Wei-Ming
;
Chiueh, Herming
;
Chen, Tsan-Jieh
;
Ho, Chia-Lun
;
Jeng, Chi
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-12-01)
Chiu, Shih-Wen
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Wang, Jen-Huo
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Chang, Kwuang-Han
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Chang, Ting-Hau
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Wang, Chia-Min
Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.
A Hardware Implementation of Real-Time Epileptic Seizure Detector on FPGA
(2011)
Chen, Tsan-Jieh
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Jeng, Chi
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Chang, Shun-Ting
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Chiueh, Herming
;
Liang, Sheng-Fu
a considerable portion of epilepsy cannot be well treated by today\'s available therapies. Brain stimulation with closed-loop seizure control was recently proposed. In our previous work, high accuracy of seizure controller (92-99% during wake-sleep states) using a microcontroller has been proposed and implemented to verify functionality of seizure detection and suppression on a freely moving rat. In this paper, the soft intellectual property (IP) of epileptic seizure detector in the implantable system on chip (SoC) for epileptic seizure control is proposed to achieve continuous real-time processing and low power consumption. All the essential macros for epileptic seizure detector are implemented and integrated in field programmable gate array (FPGA) to verify functionality and capability. The evaluation results of the prototype supported possible application of a portable and continuous real-time seizure control.
A hierarchical approach for online temporal lobe seizure detection in long-term intracranial EEG recordings
(2013-08-01)
Liang, Sheng-Fu
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Chen, Yi-Chun
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Wang, Yu-Lin
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Chen, Pin-Tzu
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Yang, Chia-Hsiang
Objective. Around 1% of the world's population is affected by epilepsy, and nearly 25% of patients cannot be treated effectively by available therapies. The presence of closed-loop seizure-triggered stimulation provides a promising solution for these patients. Realization of fast, accurate, and energy-efficient seizure detection is the key to such implants. In this study, we propose a two-stage on-line seizure detection algorithm with low-energy consumption for temporal lobe epilepsy (TLE). Approach. Multi-channel signals are processed through independent component analysis and the most representative independent component (IC) is automatically selected to eliminate artifacts. Seizure-like intracranial electroencephalogram (iEEG) segments are fast detected in the first stage of the proposed method and these seizures are confirmed in the second stage. The conditional activation of the second-stage signal processing reduces the computational effort, and hence energy, since most of the non-seizure events are filtered out in the first stage. Main results. Long-term iEEG recordings of 11 patients who suffered from TLE were analyzed via leave-one-out cross validation. The proposed method has a detection accuracy of 95.24%, a false alarm rate of 0.09/h, and an average detection delay time of 9.2 s. For the six patients with mesial TLE, a detection accuracy of 100.0%, a false alarm rate of 0.06/h, and an average detection delay time of 4.8 s can be achieved. The hierarchical approach provides a 90% energy reduction, yielding effective and energy-efficient implementation for real-time epileptic seizure detection. Significance. An on-line seizure detection method that can be applied to monitor continuous iEEG signals of patients who suffered from TLE was developed. An IC selection strategy to automatically determine the most seizure-related IC for seizure detection was also proposed. The system has advantages of (1) high detection accuracy, (2) low false alarm, (3) short detection latency, and (4) energy-efficient design for hardware implementation.
A low power pulsed edge-triggered latch for survivor memory unit of Viterbi decoder
(2006)
Su, Wei-Li
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Chiueh, Herming
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Huang, Po-Tsang
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Hwnag, Wei
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電信工程研究所
A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave register. Moreover, a stage-reduced SMU is introduced later for saving both area and power consumption. The proposed low swing static ETL and stage-reduced SMU are designed and simulated in TSMC 0.13um standard CMOS process, and the operating clock frequency is at 1GHz.
A micro-architecture simulator for multimedia stream processor
(2006)
Lin, Fang-Ju
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Chiueh, Herming
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電信工程研究所
;
Institute of Communications Engineering
Recent research has proposed using stream processors for media applications. Since a programmable Stream Processor could utilize various hardware micro-architectures for diverse media applications, decision on a suitable micro-architectures to achieve efficiencies and hardware cost is critical. In this paper, a micro-architecture simulator for stream processor is implemented. The simulator evaluate the performance of media application executed on various micro-architectures, and then to analyze the utility rate of hardware and consumption of memory. By comparing the performance of media application executed on diverse micro-architectures, the optimized hardware micro-architecture can be determined for specific application and suitable micro-architecture of Stream Processor can be implemented on later VLSI for different targeting systems.
A Multi-Channel Multi-Mode Physiological Signals Acquisition and Analysis Platform
(2013)
Lee, Sheng-Cheng
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Chen, Tsan-Jieh
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Chiueh, Herming
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電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
With the recent evolution of medical device developments, physiological signal acquisition system is widely used in health monitoring, brain machine interface, and neural prosthesis, etc. In this paper, a multi-channel multi-mode biomedical signal acquisition and analysis platform is designed and implanted. The platform includes a customized low-distortion, high signal-to-noise ratio (SNR) analog to digital converter (ADC), and a field-programmable gate array (FPGA) with an embedded soft-core of 32-bit RISC processor. A multi-mode ADC was developed to meet the resolution and bandwidth requirement of different physiological signals. The soft-core and its corresponding software was designed and implemented to provide a versatile platform for different bio-medical applications. The integration of multi-mode data converter and signal processing platform enable the turnkey solution to develop different bio-medical applications such as on-line seizure detection, heart rate monitor, physiological signals recorder, etc.
A Small Area Fully Integrated Spread-Spectrum Clock Generator with High EMI-reduction for SATA-3.0 applications
(2010)
Li, Zhen-Yu
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Chiueh, Herming
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Juang, Ying-Zong
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Chiu, Chin-Fong
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傳播研究所
In this paper, a small area spread-spectrum clock generator (SSCG) with high EMI reduction for SATA-3.0 is presented. Conventional methods use inductor-capacitance (LC) tank to fulfill the high frequency requirement for SATA-3.0. However, the monolithic inductors always occupy a large area, and required precisely characteristic for different fabrication processes. This research propose a SSCG using a ring voltage-controlled oscillators (Ring-VCO) at 6GHz operating frequency; By using the proposed Ring-VCO, the active area of SSCG is 65% of comparable LC tank implementations, and Ring-VCO is much easier to characterized for any CMOS process. In addition, a multi-stage-noise-shaping (MASH) delta-sigma modulator (Delta Sigma modulator) is used to reduce fractional spurs and quantization error for high EMI reduction. The chip is designed in TSMC 0.18um 1P6M CMOS process with active area of 500umx300um, and the simulation results consumes 60.43mW with 1.8V supply. The peak-to-peak jitter at 6GHz output of non spread-spectrum is 6.16ps, and the EMI reduction is 22.49dB with 5000ppm down spread to 5.97GHz.
A Smart Headband for Epileptic Seizure Detection
(2017-01-01)
Lin, Shih-Kai
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Lin, Yu-Shan
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Lin, Chin-Yew
;
Chiueh, Herming
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電機工程學系
Epilepsy is a common neural disorder disease; about 1.7% of the global population has epilepsy. Most patients take antiepileptic drugs to reduce their seizures. Among them, nearly one-third of the patients are drug-resistant epilepsy. The alternative treatment is the resection surgery of removing the epileptogenic zone. However, all above patients will still have some seizures, which will influence the patients' quality-of-life, and further introduce danger and inconvenience to patients and people around. This paper presents the design and develop of the smart headband for epileptic seizure detection. The headband consists of a textile headband with flexible print circuit (FPC) inside, and fabric electrodes on it. The whole system includes the following circuits: an analog front-end circuitry for electroencephalography (EEG) record, an epileptic seizure detection System-on-Chip (SoC), and a Bluetooth Low Energy (BLE) Chip. The result of designed circuits yields a compact and low-power design of smart headband for epileptic seizure detection which is suitable for wearable usage.
A Wireless Multi-Channel Physiological Signal Acquisition System-on-Chip for Wearable Devices
(2016-01-01)
Lee, Sheng-Cheng
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Lin, Yu -Shan
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Chen, Yu-Jui
;
Chiueh, Herming
;
電機工程學系
A novel wireless ExG sensor tag with a multichannel physiological signals acquisition (PSA) system is presented. The presented system, optimized for power efficiency, contains mixed-signal processor system-on-chip (SoC) and Bluetooth Low Energy (BLE) chip for real time recording and wireless transmission. The versatility of the proposed wireless ExG sensor tag is being demonstrated in several biopotential signals, such as electrocardiogram (ECG), electrooculography (EOG), and electromyogram (EMG). The ExG wireless tag with Tablet can be easily achieve 12 hours with 200mAH battery of continuous recording of ExG signals in healthcare application.
An 100MHz to 1.6GHz DLL-Based Clock Generator Using a Feedback-Switching Detector
(2010)
Lin, Ding-Guo
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Lu, Bing-Hsun
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Chiueh, Herming
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電機工程學系
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Department of Electrical and Computer Engineering
In this paper, a glitch-free DLL-based clock generator using a feedback-switching detector is proposed for a programmable power management system. The proposed circuitry utilizes feedback switching detectors to eliminate undesired glitch problem which is generated by switching feedback stage of a DLL. The clock generator can generate clock signals ranging from 100MHz to 1.6GHz. The peak to peak jitter is 23.168ps and power consumption is 37.8mW at 1.6GHz. The proposed clock generator is implemented in TSMC 0.18 mu m process and occupies only 0.039 mm(2) which is suitable for the power management systems.
An 81.6 mu W FastICA Processor for Epileptic Seizure Detection
(2015-02-01)
Yang, Chia-Hsiang
;
Shih, Yi-Hsin
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Chiueh, Herming
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電機資訊學士班
;
電子工程學系及電子研究所
To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 mu W at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 x computation speedup are achieved. The performance of the chip was verified by human dataset.